verilog 实现DES密码算法

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1．课题概述（任务、目的、要求）

本课题的任务：利用verilog语言编写出DES密码算法，并在Quartus ii上综合，得到RTL级电路。

本课题的目的：1. 通过本课题熟练掌握verilog语言，并理解DES加密原理； 2. 熟悉Quartus ii 软件使用方法。

本课题的要求：通过本课题的研究，要独立完成本实验，得到综合结果。

2．设计思路及采取的方案

思路：首先，要分析DES加密过程，深入理解DES加密原理；然后提取DES数据路径。

方案：把DES分解成多个模块，分别用verilog语言编写，最后利用顶层模块调用完成整个DES编码。

4．总结与体会（包括：设计中遇到的问题及解决过程；设计中产生的错误及原因分析；设计体会和收获）

在设计过程中，遇到不少错误，例如：在verilog语法方面，各种数据类型的定义，always语句中，“=”左边数据要定义成reg型，assign语句“=”左边要定义成wire型等等，另外在设计过程中还要把握层次，头脑中要有清晰的思路，例如DES编程，首先要分模块，然后调用，就很有讲究，DES分为三大模块：IP置换，IP逆置换，轮运算，以及密钥生成模块。我们就要层次分明去编写，最后调用，否则就会乱成一片，信号就会弄不清楚。还有在设计当中要养成良好的习惯，便于修改和查看。

5．主要参考文献

《应用密码学》 电子工业出版社 胡向东 魏琴芳编著

《密码芯片设计技术基础》 电子技术学院 戴紫彬 孙万忠 陈韬编著

《IC设计基础》 西安电子科技大学出版社 任艳颖 王彬编著

6．附录（原程序代码及注释等）

module DES_top(DES_in,DES_key,DES_out);

input [1:64] DES_in;

input [1:64] DES_key;

output [1:64] DES_out;

wire [1:64] IP_a;

wire [1:32] L1_L,L1_R,L2_L,L2_R,L3_L,L3_R,L4_L,L4_R,L5_L,L5_R,L6_L,L6_R,L7_L,L7_R,L8_L,L8_R,

L9_L,L9_R,L10_L,L10_R,L11_L,L11_R,L12_L,L12_R,L13_L,L13_R,L14_L,L14_R,L15_L,

L15_R,L16_L,L16_R;

IP IP(.IPin(DES_in),.IPout(IP_a));

wire [1:48] lkey1,lkey2,lkey3,lkey4,lkey5,lkey6,lkey7,lkey8,lkey9,lkey10,lkey11,lkey12,lkey13,lkey14,lkey15,lkey16;

key_top key_top(.key_in(DES_key),.key1(lkey1),.key2(lkey2),.key3(lkey3),.key4(lkey4),

.key5(lkey5),.key6(lkey6),.key7(lkey7),.key8(lkey8),.key9(lkey9),

.key10(lkey10),.key11(lkey11),.key12(lkey12),.key13(lkey13),.key14(lkey14),

.key15(lkey15),.key16(lkey16));

desL desL1(.inR(IP_a[33:64]),.inL(IP_a[1:32]),.KEY(lkey1),.outL(L1_L),.outR(L1_R)),

desL2(.inR(L1_L),.inL(L1_R),.KEY(lkey2),.outL(L2_L),.outR(L2_R)),

desL3(.inR(L2_L),.inL(L2_R),.KEY(lkey3),.outL(L3_L),.outR(L3_R)),

desL4(.inR(L3_L),.inL(L3_R),.KEY(lkey4),.outL(L4_L),.outR(L4_R)),

desL5(.inR(L4_L),.inL(L4_R),.KEY(lkey5),.outL(L5_L),.outR(L5_R)),

desL6(.inR(L5_L),.inL(L5_R),.KEY(lkey6),.outL(L6_L),.outR(L6_R)),

desL7(.inR(L6_L),.inL(L6_R),.KEY(lkey7),.outL(L7_L),.outR(L7_R)),

desL8(.inR(L7_L),.inL(L7_R),.KEY(lkey8),.outL(L8_L),.outR(L8_R)),

desL9(.inR(L8_L),.inL(L8_R),.KEY(lkey9),.outL(L9_L),.outR(L9_R)),

desL10(.inR(L9_L),.inL(L9_R),.KEY(lkey10),.outL(L10_L),.outR(L10_R)),

desL11(.inR(L10_L),.inL(L10_R),.KEY(lkey11),.outL(L11_L),.outR(L11_R)),

desL12(.inR(L11_L),.inL(L11_R),.KEY(lkey12),.outL(L12_L),.outR(L12_R)),

desL13(.inR(L12_L),.inL(L12_R),.KEY(lkey13),.outL(L13_L),.outR(L13_R)),

desL14(.inR(L13_L),.inL(L13_R),.KEY(lkey14),.outL(L14_L),.outR(L14_R)),

desL15(.inR(L14_L),.inL(L14_R),.KEY(lkey15),.outL(L15_L),.outR(L15_R)),

desL16(.inR(L15_L),.inL(L15_R),.KEY(lkey16),.outL(L16_R),.outR(L16_L));

IP_1 IP_1(.IP_1in({L16_L,L16_R}),.IP_1out(DES_out));

endmodule

//密钥生成模块

module key_top(key_in,key1,key2,key3,key4,key5,key6,key7,key8,key9,key10,key11,key12,key13,key14,key15,key16);

input [1:64] key_in;

output [1:48] key1,key2,key3,key4,key5,key6,key7,key8,key9,key10,key11,key12,key13,key14,key15,key16 ;

wire [1:56] i,k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14,k15,k16;

key key(.in(key_in),.C0(i[1:28]),.D0(i[29:56]));

left_shiftera left_shiftera1 (.in(i),.outM(k1)),

left_shiftera2 (.in(k1),.outM(k2)),

left_shiftera3 (.in(k8),.outM(k9)),

left_shiftera4 (.in(k15),.outM(k16));

left_shifterb left_shifterb1(.in(k2),.outN(k3)),

left_shifterb2(.in(k3),.outN(k4)),

left_shifterb3(.in(k4),.outN(k5)),

left_shifterb4(.in(k5),.outN(k6)),

left_shifterb5(.in(k6),.outN(k7)),

left_shifterb6(.in(k7),.outN(k8)),

left_shifterb7(.in(k9),.outN(k10)),

left_shifterb8(.in(k10),.outN(k11)),

left_shifterb9(.in(k11),.outN(k12)),

left_shifterb10(.in(k12),.outN(k13)),

left_shifterb11(.in(k13),.outN(k14)),

left_shifterb12(.in(k14),.outN(k15));

keys keys1(.in(k1),.out(key1)),

keys2(.in(k2),.out(key2)),

keys3(.in(k3),.out(key3)),

keys4(.in(k4),.out(key4)),

keys5(.in(k5),.out(key5)),

keys6(.in(k6),.out(key6)),

keys7(.in(k7),.out(key7)),

keys8(.in(k8),.out(key8)),

key1s9(.in(k9),.out(key9)),

keys10(.in(k10),.out(key10)),

keys11(.in(k11),.out(key11)),

keys12(.in(k12),.out(key12)),

keys13(.in(k13),.out(key13)),

keys14(.in(k14),.out(key14)),

keys15(.in(k15),.out(key15)),

keys16(.in(k16),.out(key16));

endmodule

module key (in,C0,D0);

input [1:64] in;

output [1:28] C0,D0;

wire [1:28] C0,D0;

assign C0={in[57],in[49],in[41],in[33],in[25],in[17],in[9],

in[1],in[58],in[50],in[42],in[34],in[26],in[18],

in[10],in[2],in[59],in[51],in[43],in[35],in[27],

in[19],in[11],in[3],in[60],in[52],in[44],in[36]};

assign D0={in[63],in[55],in[47],in[39],in[31],in[33],in[15],

in[7],in[62],in[54],in[46],in[38],in[30],in[22],

in[14],in[6],in[61],in[53],in[45],in[37],in[29],

in[21],in[13],in[5],in[28],in[20],in[12],in[4]};

endmodule

//移位寄存器

module left_shiftera(in,outM);

input [1:56] in;

output [1:56] outM;

wire [1:56] outM;

assign outM={in[2:56],in[1]};

endmodule

module left_shifterb(in,outN);

input [1:56] in;

output [1:56] outN;

wire [1:56] outN;

assign outN={in[3:56],in[1:2]};

endmodule

//置换选择

module keys(in,out);

input [1:56] in;

output [1:48] out;

assign out = {in[14],in[17],in[11],in[24],in[1],in[5],

in[3],in[28],in[15],in[6],in[21],in[10],

in[23],in[19],in[12],in[4],in[26],in[8],

in[16],in[7],in[27],in[20],in[13],in[2],

in[41],in[52],in[31],in[37],in[47],in[55],

in[30],in[40],in[51],in[45],in[33],in[48],

in[44],in[49],in[39],in[56],in[34],in[53],

in[46],in[42],in[50],in[36],in[29],in[32]};

endmodule

//IP置换

module IP(IPin,IPout);

input [1:64] IPin;

output [1:64] IPout;

wire [1:64] IPout;

assign IPout = {IPin[58],IPin[50],IPin[42],IPin[34],IPin[26],IPin[18],IPin[10],IPin[2],

IPin[60],IPin[52],IPin[44],IPin[36],IPin[28],IPin[20],IPin[12],IPin[4],

IPin[62],IPin[54],IPin[46],IPin[38],IPin[30],IPin[22],IPin[14],IPin[6],

IPin[64],IPin[56],IPin[48],IPin[40],IPin[32],IPin[24],IPin[16],IPin[8],

IPin[57],IPin[49],IPin[41],IPin[33],IPin[25],IPin[17],IPin[9],IPin[1],

IPin[59],IPin[51],IPin[43],IPin[35],IPin[27],IPin[19],IPin[11],IPin[3],

IPin[61],IPin[53],IPin[45],IPin[37],IPin[29],IPin[21],IPin[13],IPin[5],

IPin[63],IPin[55],IPin[47],IPin[39],IPin[31],IPin[23],IPin[15],IPin[7]};

endmodule

//IP逆置换

module IP_1(IP_1in,IP_1out);

input [1:64] IP_1in;

output [1:64] IP_1out;

wire [1:64] IP_1out;

assign IP_1out = {IP_1in[40],IP_1in[8],IP_1in[48],IP_1in[16],IP_1in[56],IP_1in[24],IP_1in[64],IP_1in[32],

IP_1in[39],IP_1in[7],IP_1in[47],IP_1in[15],IP_1in[55],IP_1in[23],IP_1in[63],IP_1in[31],

IP_1in[38],IP_1in[6],IP_1in[46],IP_1in[14],IP_1in[54],IP_1in[22],IP_1in[62],IP_1in[30],

IP_1in[37],IP_1in[5],IP_1in[45],IP_1in[13],IP_1in[53],IP_1in[21],IP_1in[61],IP_1in[29],

IP_1in[36],IP_1in[4],IP_1in[44],IP_1in[12],IP_1in[52],IP_1in[20],IP_1in[60],IP_1in[28],

IP_1in[35],IP_1in[3],IP_1in[43],IP_1in[11],IP_1in[51],IP_1in[19],IP_1in[59],IP_1in[27],

IP_1in[34],IP_1in[2],IP_1in[42],IP_1in[10],IP_1in[50],IP_1in[18],IP_1in[58],IP_1in[26],

IP_1in[33],IP_1in[1],IP_1in[41],IP_1in[9],IP_1in[49],IP_1in[17],IP_1in[57],IP_1in[25]};

endmodule

//轮运算

module desL(inR,inL,KEY,outL,outR);

input [1:32] inL,inR;

input [1:48] KEY;

output [1:32] outL, outR;

wire [1:32] t;

wire [1:32] outL,outR;

desf desf(.fin(inR),.K(KEY),.fout(t));

assign outL = inR;

assign outR = inL^t;

endmodule

//F函数

module desf(fin,K,fout);

input [1:32] fin;

input [1:48] K;

output [1:32] fout;

wire [1:48] m,n;

E_box E_box(.in(fin),.out(m));

assign n=m^K;

wire [1:32] c;

S_box S_box (.in(n),.out(c));

P P (.in(c),.out(fout));

endmodule

//置换运算P

module P(in,out);

input[1:32]in;

wire [1:32] out;

output[1:32]out;

assign out={in[16],in[7],in[20],in[21],

in[29],in[12],in[28],in[17],

in[1],in[15],in[23],in[26],

in[5],in[18],in[31],in[10],

in[2],in[8],in[24],in[14],

in[32],in[27],in[3],in[9],

in[19],in[13],in[30],in[6],

in[22],in[11],in[4],in[25]};

endmodule

//扩展E盒

module E_box(in,out);

input [1:32] in;

output [1:48] out;

wire [1:48] out;

assign out ={in[32],in[1],in[2],in[3],in[4],in[5],

in[4],in[5],in[6],in[7],in[8],in[9],

in[8],in[9],in[10],in[11],in[12],in[13],

in[12],in[13],in[14],in[15],in[16],in[17],

in[16],in[17],in[18],in[19],in[20],in[21],

in[20],in[21],in[22],in[23],in[24],in[25],

in[24],in[25],in[26],in[27],in[28],in[29],

in[28],in[29],in[30],in[31],in[32],in[1],};

endmodule

//S盒

module S_box (in,out);

input [1:48] in;

output [1:32] out;

S1 S1(in[1:6],out[1:4]);

S2 S2(in[7:12],out[5:8]);

S3 S3(in[13:18],out[9:12]);

S4 S4(in[19:24],out[13:16]);

S5 S5(in[25:30],out[17:20]);

S6 S6(in[31:36],out[21:24]);

S7 S7(in[37:42],out[25:28]);

S8 S8(in[43:48],out[29:32]);

endmodule

module S1(in,out);

input [1:6] in;

reg [1:4] out;

output [1:4] out;

always @ (in[1:6])

begin

case(in[1:6])

6'b000000 : out[1:4] = 4'd14;

6'b000001 : out[1:4] = 4'd0;

6'b000010 : out[1:4] = 4'd4;

6'b000011 : out[1:4] = 4'd15;

6'b000100 : out[1:4] = 4'd13;

6'b000101 : out[1:4] = 4'd7;

6'b000110 : out[1:4] = 4'd1;

6'b000111 : out[1:4] = 4'd4;

6'b001000 : out[1:4] = 4'd2;

6'b001001 : out[1:4] = 4'd14;

6'b001010 : out[1:4] = 4'd15;

6'b001011 : out[1:4] = 4'd2;

6'b001100 : out[1:4] = 4'd11;

6'b001101 : out[1:4] = 4'd13;

6'b001110 : out[1:4] = 4'd8;

6'b001111 : out[1:4] = 4'd1;

6'b010000 : out[1:4] = 4'd3;

6'b010001 : out[1:4] = 4'd10;

6'b010010 : out[1:4] = 4'd10;

6'b010011 : out[1:4] = 4'd6;

6'b010100 : out[1:4] = 4'd6;

6'b010101 : out[1:4] = 4'd12;

6'b010110 : out[1:4] = 4'd12;

6'b010111 : out[1:4] = 4'd11;

6'b011000 : out[1:4] = 4'd5;

6'b011001 : out[1:4] = 4'd9;

6'b011010 : out[1:4] = 4'd9;

6'b011011 : out[1:4] = 4'd5;

6'b011100 : out[1:4] = 4'd0;

6'b011101 : out[1:4] = 4'd3;

6'b011110 : out[1:4] = 4'd7;

6'b011111 : out[1:4] = 4'd8;

6'b100000 : out[1:4] = 4'd4;

6'b100001 : out[1:4] = 4'd15;

6'b100010 : out[1:4] = 4'd1;

6'b100011 : out[1:4] = 4'd12;

6'b100100 : out[1:4] = 4'd14;

6'b100101 : out[1:4] = 4'd8;

6'b100110 : out[1:4] = 4'd8;

6'b100111 : out[1:4] = 4'd2;

6'b101000 : out[1:4] = 4'd13;

6'b101001 : out[1:4] = 4'd4;

6'b101010 : out[1:4] = 4'd6;

6'b101011 : out[1:4] = 4'd9;

6'b101100 : out[1:4] = 4'd2;

6'b101101 : out[1:4] = 4'd1;

6'b101110 : out[1:4] = 4'd11;

6'b101111 : out[1:4] = 4'd7;

6'b110000 : out[1:4] = 4'd15;

6'b110001 : out[1:4] = 4'd5;

6'b110010 : out[1:4] = 4'd12;

6'b110011 : out[1:4] = 4'd11;

6'b110100 : out[1:4] = 4'd9;

6'b110101 : out[1:4] = 4'd3;

6'b110110 : out[1:4] = 4'd7;

6'b110111 : out[1:4] = 4'd14;

6'b111000 : out[1:4] = 4'd3;

6'b111001 : out[1:4] = 4'd10;

6'b111010 : out[1:4] = 4'd10;

6'b111011 : out[1:4] = 4'd0;

6'b111100 : out[1:4] = 4'd5;

6'b111101 : out[1:4] = 4'd6;

6'b111110 : out[1:4] = 4'd0;

6'b111111 : out[1:4] = 4'd13;

endcase

end

endmodule

module S2(in,out);

input [1:6] in;

reg [1:4] out;

output [1:4] out;

always @ (in[1:6])

begin

case(in[1:6])

6'b000000 : out[1:4] = 4'd15;

6'b000001 : out[1:4] = 4'd3;

6'b000010 : out[1:4] = 4'd1;

6'b000011 : out[1:4] = 4'd13;

6'b000100 : out[1:4] = 4'd8;

6'b000101 : out[1:4] = 4'd4;

6'b000110 : out[1:4] = 4'd14;

6'b000111 : out[1:4] = 4'd7;

6'b001000 : out[1:4] = 4'd6;

6'b001001 : out[1:4] = 4'd15;

6'b001010 : out[1:4] = 4'd11;

6'b001011 : out[1:4] = 4'd2;

6'b001100 : out[1:4] = 4'd3;

6'b001101 : out[1:4] = 4'd8;

6'b001110 : out[1:4] = 4'd4;

6'b001111 : out[1:4] = 4'd14;

6'b010000 : out[1:4] = 4'd9;

6'b010001 : out[1:4] = 4'd12;

6'b010010 : out[1:4] = 4'd7;

6'b010011 : out[1:4] = 4'd0;

6'b010100 : out[1:4] = 4'd2;

6'b010101 : out[1:4] = 4'd1;

6'b010110 : out[1:4] = 4'd13;

6'b010111 : out[1:4] = 4'd10;

6'b011000 : out[1:4] = 4'd12;

6'b011001 : out[1:4] = 4'd6;

6'b011010 : out[1:4] = 4'd0;

6'b011011 : out[1:4] = 4'd9;

6'b011100 : out[1:4] = 4'd5;

6'b011101 : out[1:4] = 4'd11;

6'b011110 : out[1:4] = 4'd10;

6'b011111 : out[1:4] = 4'd5;

6'b100000 : out[1:4] = 4'd0;

6'b100001 : out[1:4] = 4'd13;

6'b100010 : out[1:4] = 4'd14;

6'b100011 : out[1:4] = 4'd8;

6'b100100 : out[1:4] = 4'd7;

6'b100101 : out[1:4] = 4'd10;

6'b100110 : out[1:4] = 4'd11;

6'b100111 : out[1:4] = 4'd1;

6'b101000 : out[1:4] = 4'd10;

6'b101001 : out[1:4] = 4'd3;

6'b101010 : out[1:4] = 4'd4;

6'b101011 : out[1:4] = 4'd15;

6'b101100 : out[1:4] = 4'd13;

6'b101101 : out[1:4] = 4'd4;

6'b101110 : out[1:4] = 4'd1;

6'b101111 : out[1:4] = 4'd2;

6'b110000 : out[1:4] = 4'd5;

6'b110001 : out[1:4] = 4'd11;

6'b110010 : out[1:4] = 4'd8;

6'b110011 : out[1:4] = 4'd6;

6'b110100 : out[1:4] = 4'd12;

6'b110101 : out[1:4] = 4'd7;

6'b110110 : out[1:4] = 4'd6;

6'b110111 : out[1:4] = 4'd12;

6'b111000 : out[1:4] = 4'd9;

6'b111001 : out[1:4] = 4'd0;

6'b111010 : out[1:4] = 4'd3;

6'b111011 : out[1:4] = 4'd5;

6'b111100 : out[1:4] = 4'd2;

6'b111101 : out[1:4] = 4'd14;

6'b111110 : out[1:4] = 4'd15;

6'b111111 : out[1:4] = 4'd9;

endcase

end

endmodule

module S3(in,out);

input [1:6] in;

reg [1:4] out;

output [1:4] out;

always @ (in[1:6])

begin

case(in[1:6])

6'b000000 : out[1:4] = 4'd10;

6'b000001 : out[1:4] = 4'd13;

6'b000010 : out[1:4] = 4'd0;

6'b000011 : out[1:4] = 4'd7;

6'b000100 : out[1:4] = 4'd9;

6'b000101 : out[1:4] = 4'd0;

6'b000110 : out[1:4] = 4'd14;

6'b000111 : out[1:4] = 4'd9;

6'b001000 : out[1:4] = 4'd6;

6'b001001 : out[1:4] = 4'd3;

6'b001010 : out[1:4] = 4'd3;

6'b001011 : out[1:4] = 4'd4;

6'b001100 : out[1:4] = 4'd15;

6'b001101 : out[1:4] = 4'd6;

6'b001110 : out[1:4] = 4'd5;

6'b001111 : out[1:4] = 4'd10;

6'b010000 : out[1:4] = 4'd1;

6'b010001 : out[1:4] = 4'd2;

6'b010010 : out[1:4] = 4'd13;

6'b010011 : out[1:4] = 4'd8;

6'b010100 : out[1:4] = 4'd12;

6'b010101 : out[1:4] = 4'd5;

6'b010110 : out[1:4] = 4'd7;

6'b010111 : out[1:4] = 4'd14;

6'b011000 : out[1:4] = 4'd11;

6'b011001 : out[1:4] = 4'd12;

6'b011010 : out[1:4] = 4'd4;

6'b011011 : out[1:4] = 4'd11;

6'b011100 : out[1:4] = 4'd2;

6'b011101 : out[1:4] = 4'd15;

6'b011110 : out[1:4] = 4'd8;

6'b011111 : out[1:4] = 4'd1;

6'b100000 : out[1:4] = 4'd13;

6'b100001 : out[1:4] = 4'd1;

6'b100010 : out[1:4] = 4'd6;

6'b100011 : out[1:4] = 4'd10;

6'b100100 : out[1:4] = 4'd4;

6'b100101 : out[1:4] = 4'd13;

6'b100110 : out[1:4] = 4'd9;

6'b100111 : out[1:4] = 4'd0;

6'b101000 : out[1:4] = 4'd8;

6'b101001 : out[1:4] = 4'd6;

6'b101010 : out[1:4] = 4'd15;

6'b101011 : out[1:4] = 4'd9;

6'b101100 : out[1:4] = 4'd3;

6'b101101 : out[1:4] = 4'd8;

6'b101110 : out[1:4] = 4'd0;

6'b101111 : out[1:4] = 4'd7;

6'b110000 : out[1:4] = 4'd11;

6'b110001 : out[1:4] = 4'd4;

6'b110010 : out[1:4] = 4'd1;

6'b110011 : out[1:4] = 4'd15;

6'b110100 : out[1:4] = 4'd2;

6'b110101 : out[1:4] = 4'd14;

6'b110110 : out[1:4] = 4'd12;

6'b110111 : out[1:4] = 4'd3;

6'b111000 : out[1:4] = 4'd5;

6'b111001 : out[1:4] = 4'd11;

6'b111010 : out[1:4] = 4'd10;

6'b111011 : out[1:4] = 4'd5;

6'b111100 : out[1:4] = 4'd14;

6'b111101 : out[1:4] = 4'd2;

6'b111110 : out[1:4] = 4'd7;

6'b111111 : out[1:4] = 4'd12;

endcase

end

endmodule

module S4(in,out);

input [1:6] in;

reg [1:4] out;

output [1:4] out;

always @ (in[1:6])

begin

case(in[1:6])

6'b000000 : out[1:4] = 4'd7;

6'b000001 : out[1:4] = 4'd13;

6'b000010 : out[1:4] = 4'd13;

6'b000011 : out[1:4] = 4'd8;

6'b000100 : out[1:4] = 4'd14;

6'b000101 : out[1:4] = 4'd11;

6'b000110 : out[1:4] = 4'd3;

6'b000111 : out[1:4] = 4'd5;

6'b001000 : out[1:4] = 4'd0;

6'b001001 : out[1:4] = 4'd6;

6'b001010 : out[1:4] = 4'd6;

6'b001011 : out[1:4] = 4'd15;

6'b001100 : out[1:4] = 4'd9;

6'b001101 : out[1:4] = 4'd0;

6'b001110 : out[1:4] = 4'd10;

6'b001111 : out[1:4] = 4'd3;

6'b010000 : out[1:4] = 4'd1;

6'b010001 : out[1:4] = 4'd4;

6'b010010 : out[1:4] = 4'd2;

6'b010011 : out[1:4] = 4'd7;

6'b010100 : out[1:4] = 4'd8;

6'b010101 : out[1:4] = 4'd2;

6'b010110 : out[1:4] = 4'd5;

6'b010111 : out[1:4] = 4'd12;

6'b011000 : out[1:4] = 4'd11;

6'b011001 : out[1:4] = 4'd1;

6'b011010 : out[1:4] = 4'd12;

6'b011011 : out[1:4] = 4'd10;

6'b011100 : out[1:4] = 4'd4;

6'b011101 : out[1:4] = 4'd14;

6'b011110 : out[1:4] = 4'd15;

6'b011111 : out[1:4] = 4'd9;

6'b100000 : out[1:4] = 4'd10;

6'b100001 : out[1:4] = 4'd3;

6'b100010 : out[1:4] = 4'd6;

6'b100011 : out[1:4] = 4'd15;

6'b100100 : out[1:4] = 4'd9;

6'b100101 : out[1:4] = 4'd0;

6'b100110 : out[1:4] = 4'd0;

6'b100111 : out[1:4] = 4'd6;

6'b101000 : out[1:4] = 4'd12;

6'b101001 : out[1:4] = 4'd10;

6'b101010 : out[1:4] = 4'd11;

6'b101011 : out[1:4] = 4'd1;

6'b101100 : out[1:4] = 4'd7;

6'b101101 : out[1:4] = 4'd13;

6'b101110 : out[1:4] = 4'd13;

6'b101111 : out[1:4] = 4'd8;

6'b110000 : out[1:4] = 4'd15;

6'b110001 : out[1:4] = 4'd9;

6'b110010 : out[1:4] = 4'd1;

6'b110011 : out[1:4] = 4'd4;

6'b110100 : out[1:4] = 4'd3;

6'b110101 : out[1:4] = 4'd5;

6'b110110 : out[1:4] = 4'd14;

6'b110111 : out[1:4] = 4'd11;

6'b111000 : out[1:4] = 4'd5;

6'b111001 : out[1:4] = 4'd12;

6'b111010 : out[1:4] = 4'd2;

6'b111011 : out[1:4] = 4'd7;

6'b111100 : out[1:4] = 4'd8;

6'b111101 : out[1:4] = 4'd2;

6'b111110 : out[1:4] = 4'd4;

6'b111111 : out[1:4] = 4'd14;

endcase

end

endmodule

module S5(in,out);

input [1:6] in;

reg [1:4] out;

output [1:4] out;

always @ (in[1:6])

begin

case(in[1:6])

6'b000000 : out[1:4] = 4'd2;

6'b000001 : out[1:4] = 4'd14;

6'b000010 : out[1:4] = 4'd12;

6'b000011 : out[1:4] = 4'd11;

6'b000100 : out[1:4] = 4'd4;

6'b000101 : out[1:4] = 4'd2;

6'b000110 : out[1:4] = 4'd1;

6'b000111 : out[1:4] = 4'd12;

6'b001000 : out[1:4] = 4'd7;

6'b001001 : out[1:4] = 4'd4;

6'b001010 : out[1:4] = 4'd10;

6'b001011 : out[1:4] = 4'd7;

6'b001100 : out[1:4] = 4'd11;

6'b001101 : out[1:4] = 4'd13;

6'b001110 : out[1:4] = 4'd6;

6'b001111 : out[1:4] = 4'd1;

6'b010000 : out[1:4] = 4'd8;

6'b010001 : out[1:4] = 4'd5;

6'b010010 : out[1:4] = 4'd5;

6'b010011 : out[1:4] = 4'd0;

6'b010100 : out[1:4] = 4'd3;

6'b010101 : out[1:4] = 4'd15;

6'b010110 : out[1:4] = 4'd15;

6'b010111 : out[1:4] = 4'd10;

6'b011000 : out[1:4] = 4'd13;

6'b011001 : out[1:4] = 4'd3;

6'b011010 : out[1:4] = 4'd0;

6'b011011 : out[1:4] = 4'd9;

6'b011100 : out[1:4] = 4'd14;

6'b011101 : out[1:4] = 4'd8;

6'b011110 : out[1:4] = 4'd9;

6'b011111 : out[1:4] = 4'd6;

6'b100000 : out[1:4] = 4'd4;

6'b100001 : out[1:4] = 4'd11;

6'b100010 : out[1:4] = 4'd2;

6'b100011 : out[1:4] = 4'd8;

6'b100100 : out[1:4] = 4'd1;

6'b100101 : out[1:4] = 4'd12;

6'b100110 : out[1:4] = 4'd11;

6'b100111 : out[1:4] = 4'd7;

6'b101000 : out[1:4] = 4'd10;

6'b101001 : out[1:4] = 4'd1;

6'b101010 : out[1:4] = 4'd13;

6'b101011 : out[1:4] = 4'd14;

6'b101100 : out[1:4] = 4'd7;

6'b101101 : out[1:4] = 4'd2;

6'b101110 : out[1:4] = 4'd8;

6'b101111 : out[1:4] = 4'd13;

6'b110000 : out[1:4] = 4'd15;

6'b110001 : out[1:4] = 4'd6;

6'b110010 : out[1:4] = 4'd9;

6'b110011 : out[1:4] = 4'd15;

6'b110100 : out[1:4] = 4'd12;

6'b110101 : out[1:4] = 4'd0;

6'b110110 : out[1:4] = 4'd5;

6'b110111 : out[1:4] = 4'd9;

6'b111000 : out[1:4] = 4'd6;

6'b111001 : out[1:4] = 4'd10;

6'b111010 : out[1:4] = 4'd3;

6'b111011 : out[1:4] = 4'd4;

6'b111100 : out[1:4] = 4'd0;

6'b111101 : out[1:4] = 4'd5;

6'b111110 : out[1:4] = 4'd14;

6'b111111 : out[1:4] = 4'd3;

endcase

end

endmodule

module S6(in,out);

input [1:6] in;

reg [1:4] out;

output [1:4] out;

always @ (in[1:6])

begin

case(in[1:6])

6'b000000 : out[1:4] = 4'd12;

6'b000001 : out[1:4] = 4'd10;

6'b000010 : out[1:4] = 4'd1;

6'b000011 : out[1:4] = 4'd15;

6'b000100 : out[1:4] = 4'd10;

6'b000101 : out[1:4] = 4'd4;

6'b000110 : out[1:4] = 4'd15;

6'b000111 : out[1:4] = 4'd2;

6'b001000 : out[1:4] = 4'd9;

6'b001001 : out[1:4] = 4'd7;

6'b001010 : out[1:4] = 4'd2;

6'b001011 : out[1:4] = 4'd12;

6'b001100 : out[1:4] = 4'd6;

6'b001101 : out[1:4] = 4'd9;

6'b001110 : out[1:4] = 4'd8;

6'b001111 : out[1:4] = 4'd5;

6'b010000 : out[1:4] = 4'd0;

6'b010001 : out[1:4] = 4'd6;

6'b010010 : out[1:4] = 4'd13;

6'b010011 : out[1:4] = 4'd1;

6'b010100 : out[1:4] = 4'd3;

6'b010101 : out[1:4] = 4'd13;

6'b010110 : out[1:4] = 4'd4;

6'b010111 : out[1:4] = 4'd14;

6'b011000 : out[1:4] = 4'd14;

6'b011001 : out[1:4] = 4'd0;

6'b011010 : out[1:4] = 4'd7;

6'b011011 : out[1:4] = 4'd11;

6'b011100 : out[1:4] = 4'd5;

6'b011101 : out[1:4] = 4'd3;

6'b011110 : out[1:4] = 4'd11;

6'b011111 : out[1:4] = 4'd8;

6'b100000 : out[1:4] = 4'd9;

6'b100001 : out[1:4] = 4'd4;

6'b100010 : out[1:4] = 4'd14;

6'b100011 : out[1:4] = 4'd3;

6'b100100 : out[1:4] = 4'd15;

6'b100101 : out[1:4] = 4'd2;

6'b100110 : out[1:4] = 4'd5;

6'b100111 : out[1:4] = 4'd12;

6'b101000 : out[1:4] = 4'd2;

6'b101001 : out[1:4] = 4'd9;

6'b101010 : out[1:4] = 4'd8;

6'b101011 : out[1:4] = 4'd5;

6'b101100 : out[1:4] = 4'd12;

6'b101101 : out[1:4] = 4'd15;

6'b101110 : out[1:4] = 4'd3;

6'b101111 : out[1:4] = 4'd10;

6'b110000 : out[1:4] = 4'd7;

6'b110001 : out[1:4] = 4'd11;

6'b110010 : out[1:4] = 4'd0;

6'b110011 : out[1:4] = 4'd14;

6'b110100 : out[1:4] = 4'd4;

6'b110101 : out[1:4] = 4'd1;

6'b110110 : out[1:4] = 4'd10;

6'b110111 : out[1:4] = 4'd7;

6'b111000 : out[1:4] = 4'd1;

6'b111001 : out[1:4] = 4'd6;

6'b111010 : out[1:4] = 4'd13;

6'b111011 : out[1:4] = 4'd0;

6'b111100 : out[1:4] = 4'd11;

6'b111101 : out[1:4] = 4'd8;

6'b111110 : out[1:4] = 4'd6;

6'b111111 : out[1:4] = 4'd13;

endcase

end

endmodule

module S7(in,out);

input [1:6] in;

reg [1:4] out;

output [1:4] out;

always @ (in[1:6])

begin

case(in[1:6])

6'b000000 : out[1:4] = 4'd4;

6'b000001 : out[1:4] = 4'd13;

6'b000010 : out[1:4] = 4'd11;

6'b000011 : out[1:4] = 4'd0;

6'b000100 : out[1:4] = 4'd2;

6'b000101 : out[1:4] = 4'd11;

6'b000110 : out[1:4] = 4'd14;

6'b000111 : out[1:4] = 4'd7;

6'b001000 : out[1:4] = 4'd15;

6'b001001 : out[1:4] = 4'd4;

6'b001010 : out[1:4] = 4'd0;

6'b001011 : out[1:4] = 4'd9;

6'b001100 : out[1:4] = 4'd8;

6'b001101 : out[1:4] = 4'd1;

6'b001110 : out[1:4] = 4'd13;

6'b001111 : out[1:4] = 4'd10;

6'b010000 : out[1:4] = 4'd3;

6'b010001 : out[1:4] = 4'd14;

6'b010010 : out[1:4] = 4'd12;

6'b010011 : out[1:4] = 4'd3;

6'b010100 : out[1:4] = 4'd9;

6'b010101 : out[1:4] = 4'd5;

6'b010110 : out[1:4] = 4'd7;

6'b010111 : out[1:4] = 4'd12;

6'b011000 : out[1:4] = 4'd5;

6'b011001 : out[1:4] = 4'd2;

6'b011010 : out[1:4] = 4'd10;

6'b011011 : out[1:4] = 4'd15;

6'b011100 : out[1:4] = 4'd6;

6'b011101 : out[1:4] = 4'd8;

6'b011110 : out[1:4] = 4'd1;

6'b011111 : out[1:4] = 4'd6;

6'b100000 : out[1:4] = 4'd1;

6'b100001 : out[1:4] = 4'd6;

6'b100010 : out[1:4] = 4'd4;

6'b100011 : out[1:4] = 4'd11;

6'b100100 : out[1:4] = 4'd11;

6'b100101 : out[1:4] = 4'd13;

6'b100110 : out[1:4] = 4'd13;

6'b100111 : out[1:4] = 4'd8;

6'b101000 : out[1:4] = 4'd12;

6'b101001 : out[1:4] = 4'd1;

6'b101010 : out[1:4] = 4'd3;

6'b101011 : out[1:4] = 4'd4;

6'b101100 : out[1:4] = 4'd7;

6'b101101 : out[1:4] = 4'd10;

6'b101110 : out[1:4] = 4'd14;

6'b101111 : out[1:4] = 4'd7;

6'b110000 : out[1:4] = 4'd10;

6'b110001 : out[1:4] = 4'd9;

6'b110010 : out[1:4] = 4'd15;

6'b110011 : out[1:4] = 4'd5;

6'b110100 : out[1:4] = 4'd6;

6'b110101 : out[1:4] = 4'd0;

6'b110110 : out[1:4] = 4'd8;

6'b110111 : out[1:4] = 4'd15;

6'b111000 : out[1:4] = 4'd0;

6'b111001 : out[1:4] = 4'd14;

6'b111010 : out[1:4] = 4'd5;

6'b111011 : out[1:4] = 4'd2;

6'b111100 : out[1:4] = 4'd9;

6'b111101 : out[1:4] = 4'd3;

6'b111110 : out[1:4] = 4'd2;

6'b111111 : out[1:4] = 4'd12;

endcase

end

endmodule

module S8(in,out);

input [1:6] in;

reg [1:4] out;

output [1:4] out;

always @ (in[1:6])

begin

case(in[1:6])

6'b000000 : out[1:4] = 4'd13;

6'b000001 : out[1:4] = 4'd1;

6'b000010 : out[1:4] = 4'd2;

6'b000011 : out[1:4] = 4'd15;

6'b000100 : out[1:4] = 4'd8;

6'b000101 : out[1:4] = 4'd13;

6'b000110 : out[1:4] = 4'd4;

6'b000111 : out[1:4] = 4'd8;

6'b001000 : out[1:4] = 4'd6;

6'b001001 : out[1:4] = 4'd10;

6'b001010 : out[1:4] = 4'd15;

6'b001011 : out[1:4] = 4'd3;

6'b001100 : out[1:4] = 4'd11;

6'b001101 : out[1:4] = 4'd7;

6'b001110 : out[1:4] = 4'd1;

6'b001111 : out[1:4] = 4'd4;

6'b010000 : out[1:4] = 4'd10;

6'b010001 : out[1:4] = 4'd12;

6'b010010 : out[1:4] = 4'd9;

6'b010011 : out[1:4] = 4'd5;

6'b010100 : out[1:4] = 4'd3;

6'b010101 : out[1:4] = 4'd6;

6'b010110 : out[1:4] = 4'd14;

6'b010111 : out[1:4] = 4'd11;

6'b011000 : out[1:4] = 4'd5;

6'b011001 : out[1:4] = 4'd0;

6'b011010 : out[1:4] = 4'd0;

6'b011011 : out[1:4] = 4'd14;

6'b011100 : out[1:4] = 4'd12;

6'b011101 : out[1:4] = 4'd9;

6'b011110 : out[1:4] = 4'd7;

6'b011111 : out[1:4] = 4'd2;

6'b100000 : out[1:4] = 4'd7;

6'b100001 : out[1:4] = 4'd2;

6'b100010 : out[1:4] = 4'd11;

6'b100011 : out[1:4] = 4'd1;

6'b100100 : out[1:4] = 4'd4;

6'b100101 : out[1:4] = 4'd14;

6'b100110 : out[1:4] = 4'd1;

6'b100111 : out[1:4] = 4'd7;

6'b101000 : out[1:4] = 4'd9;

6'b101001 : out[1:4] = 4'd4;

6'b101010 : out[1:4] = 4'd12;

6'b101011 : out[1:4] = 4'd10;

6'b101100 : out[1:4] = 4'd14;

6'b101101 : out[1:4] = 4'd8;

6'b101110 : out[1:4] = 4'd2;

6'b101111 : out[1:4] = 4'd13;

6'b110000 : out[1:4] = 4'd0;

6'b110001 : out[1:4] = 4'd15;

6'b110010 : out[1:4] = 4'd6;

6'b110011 : out[1:4] = 4'd12;

6'b110100 : out[1:4] = 4'd10;

6'b110101 : out[1:4] = 4'd9;

6'b110110 : out[1:4] = 4'd13;

6'b110111 : out[1:4] = 4'd0;

6'b111000 : out[1:4] = 4'd15;

6'b111001 : out[1:4] = 4'd3;

6'b111010 : out[1:4] = 4'd3;

6'b111011 : out[1:4] = 4'd5;

6'b111100 : out[1:4] = 4'd5;

6'b111101 : out[1:4] = 4'd6;

6'b111110 : out[1:4] = 4'd8;

6'b111111 : out[1:4] = 4'd11;

endcase

end

endmodule