How to inline ASM in C (gcc)

How to inline ASM in C (gcc)

我已经测试过，这是个helloworld，在屏幕上打印Hello World，运行正常：
Code:
#include <pspkernel.h>
#include <pspdebug.h>

PSP_MODULE_INFO("Hello World", 0, 1, 1);

int main(void) {
   char *msg = "Hello world!/n";
   pspDebugScreenInit();
   asm("lui $4, %%hi(%0)/n"
   "jal pspDebugScreenPrintf/n"
   "addiu $4,$4,%%lo(%0)/n"
   "nop/n"
   : : "g" (msg));
   return 0;
}

lui, load upper immediate.
$4, $4 will be loaded later.
%%hi, this will grab the upper 16bits of (val).
$0, this is this first argument passed into the function.
jal, jump and load.
pspDebugScreenPrintf, the jal loads pspDebugScreenPrintf and that prints $4.
addiu, add immmediate unsigned.
$4,$4,%%lo(%0), $4 + %%lo(%0) (lower 16 bits of the first arguement passed into the function) = $4.
nop, no operation. This means that instead of setting $4 after jal, you can set before. This is used for aligning code.
: : "g" (msg));, loads the variable msg ($0) and ends the asm function. This requires -02 on gcc, if that isnt by default.


makefile 这样写
TARGET = hello
OBJS = main.o

CFLAGS = -O2 -G0 -Wall
CXXFLAGS = $(CFLAGS) -fno-exceptions -fno-rtti
ASFLAGS = $(CFLAGS)

EXTRA_TARGETS = EBOOT.PBP
PSP_EBOOT_TITLE = Hello World in ASM

PSPSDK=$(shell psp-config --pspsdk-path)
include $(PSPSDK)/lib/build.mak

更详细的指令资料


MIPS R4000 Microprocessor Instruction List
This information was taken from the MIPS R4000 Microprocessor User Manual

Load and Store
Load and store instructions move data between memory and general registers. They are all immediate (I-type) instructions, since the only addressing mode supported is base register plus 16-bit, signed immediate offset.

Load and Store Instructions

OpCode  Description
LB          Load byte  
LBU        Load byte unsigned  
LH          Load halfword  
LHU        Load halfword unsigned  
LW         Load word  
LWL       Load word left  
LWR      Load word right  
SB         Store byte  
SH         Store halfword  
SW        Store word  
SWL      Store word left  
SWR      Store word right  


Computational
Computation instructions perform arithmetic, logical, shift, multiply and divide operation on values in registers. They include register (R-type, in which both the operands and the result are stored in registers) and immediate (I-type, in which one operand is a 16-bit immediate value) formats.

Arithmetic Instructions (ALU Immediate)

OpCode  Description
ADDI      Add immediate  
ADDIU    Add immmediate unsigned  
SLTI       Set on less than immediate  
SLTIU     Set on less than immediate unsigned  
ANDI      AND immediate  
ORI        OR immediate  
XORI      Exclusive OR immediate  
LUI        Load upper immediate  


Arithmetic (3-Operand, R-Type)

OpCode  Description  
ADD       Add  
ADDU     Add unsigned  
SUB       Subtract  
SUBU     Subtract unsigned  
SLT       Set on less than  
SLYU     Set on less than unsigned  
AND      AND  
OR        OR  
XOR      Exclusive OR  
NOR      NOR  


Multiply and Divide Instructions

OpCode  Description  
MULT      Multiply  
MULTU    Multiply unsigned  
DIV         Divide  
DIVU       Divide unsigned  
MFHI       Move from HI  
MTHI      Move to HI  
MFLO      Move from LO  
MTLO     Move to LO  


Jump and Branch
Jump and branch instructions change the control flow of a program. Jumps are always made to a paged, absolute address formed by combining a 26-bit target address with the high-order bits of the Program Counter (J-type format) or register address (R-type format). Branches have 16-bit offsets relative to the program counter (I-type). Jump And Link instructions save their return address in register 31.

Jump and Branch Instructions

OpCode  Description  
J              Jump  
JAL          Jump and link  
JR            Jump and register  
JALR        Jump and link register  
BEQ          Branch on equal  
BNE          Branch on not equal  
BLEZ        Branch on less than or equal to zero  
BGTZ       Branch on greater than zero  
BLTZ       Branch on less than zero  
BGEZ       Branch on greater thn or equal to zero  
BLTZAL   Branch on less than zero and link  
BGEZAL   Branch on greater than or equal to zero and link  


Shift Instructions

OpCode  Description  
SLL          Shift left logical  
SRL         Shift right logical  
SRA         Shit right artithmetic  
SLLV        Shift left logical veriable  
SRLV       Shift right logical variable  
SRAV      Shift right artithmetic variable  


Coprocessor
Coprocessor instructions perform operations in the coprocessors. Coprocessor load and store instructions are I-type.
Coprocessor 0 (system coprocessor)
Coprocessor 0 (system coprocessor) instructions perform operations on CP0 registers to control the memory management and exception handling facilities of the processor.

Coprocessor Instructions

OpCode  Description  
LWCz       Load word to coprocessor z  
SWCz       Store word from coprocessor z  
MTCz       Move to coprocessor z  
MFCz       Move from coprocessor z  
CTCz       Move control to coprocessor z  
CFCz       Move control from coprocessor z  
COPz      Coprocessor operation z  
BCzT      Branch on coprocessor z true  
BCzF      Branch on coprocessor z false  


Special
Special instructions perform system calls and breakpoint operations. These instructions are always R-type.
Special Instructions

OpCode  Description  
SYSCALL   System call  
BREAK      Break

 

MIPS 汇编资料
MIPS ASM Tutorial
http://kedem.cs.duke.edu/cps104/Handouts/MIPS-asm.pdf
MIPS USER BOOK
http://hitmen.c02.at/files/docs/psp/R4400_Uman_book_Ed2.pdf