FPGA之按钮防抖动设计的verilog实现

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方法一：clk是已经分频好的时钟。

module Light( in_key,out_key,clk,clr); input in_key,clk,clr; output out_key; reg delay1,delay2,delay3; always@( posedge clk)//CLK 50M beginif(clr)begindelay1  <= 0;delay2  <= 0;delay3  <= 0;     end    else    begin        delay1  <= in_key;         delay2  <= delay1;delay3  <= delay2;    end end  assign out_key = delay1&delay2&delay3; endmodule

方法二：

http://blog.csdn.net/ywhfdl/article/details/7552289 这个做法是自己做的时钟，不过这个代码风格比较差，不建议这样写。里面没有加复位，整个混乱。

方法三：

module key_debounce(input key,clk,clr,output key_changed2    );wire key_changed1;reg [20:0] count;//reg [2:0] count; //for simulationreg sample1, sample_locked1, sample2, sample_locked2;always @(posedge clk or posedge clr)if(clr) sample1 <= 0;else sample1 <= key;always @(posedge clk or posedge clr)if(clr) sample_locked1 <= 0;else sample_locked1 <= sample1;assign key_changed1 = ~sample_locked1 & sample1;always @(posedge clk or posedge clr)if(clr) count <= 0;else if(key_changed1) count <= 0;else count <= count + 1;always @(posedge clk or posedge clr)if(clr) sample2 <= 0;else if(count == 2000000)//else if(count == 2) // for simulationsample2 <= key;always @(posedge clk or posedge clr)if(clr) sample_locked2 <= 0;else sample_locked2 <= sample2;assign key_changed2 = ~sample_locked2 & sample2;endmodule

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