linux kernel4版本 am335x gpmc 总线 dtb编写
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&gpmc {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&nandflash_pins_default>;
pinctrl-1 = <&nandflash_pins_sleep>;
ranges = <0 0 0x08000000 0x2000000>,/* CS0: NAND */
<2 0 0x10000000 0x1000000>,/* CS2: DUART */
<3 0 0x11000000 0x1000000>;/* CS3: DUART */
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "rootfs";
reg = <0x00000000 0x20000000>;
};
};
uart@3,0 {
compatible = "ns16550a";
reg = <3 0 8>; /* CS3, offset 0, IO size 8 */
bank-width = <2>;
reg-shift = <1>;
reg-io-width = <1>;
interrupt-parent = <&gpio0>;
interrupts = <8 8>; /* gpio102 */
clock-frequency = <1843200>;
current-speed = <115200>;
gpmc,mux-add-data = <0>;
gpmc,device-width = <1>;
gpmc,wait-pin = <1>;
gpmc,cycle2cycle-samecsen = <1>;
gpmc,cycle2cycle-diffcsen = <1>;
gpmc,cs-on-ns = <5>;
gpmc,cs-rd-off-ns = <155>;
gpmc,cs-wr-off-ns = <155>;
gpmc,adv-on-ns = <15>;
gpmc,adv-rd-off-ns = <40>;
gpmc,adv-wr-off-ns = <40>;
gpmc,oe-on-ns = <45>;
gpmc,oe-off-ns = <145>;
gpmc,we-on-ns = <45>;
gpmc,we-off-ns = <145>;
gpmc,rd-cycle-ns = <155>;
gpmc,wr-cycle-ns = <155>;
gpmc,access-ns = <145>;
gpmc,page-burst-access-ns = <20>;
gpmc,bus-turnaround-ns = <20>;
gpmc,cycle2cycle-delay-ns = <20>;
gpmc,wait-monitoring-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-data-mux-bus-ns = <45>;
gpmc,wr-access-ns = <145>;
};
uart@3,1 {
compatible = "ns16550a";
reg = <3 0x8 8>; /* CS3, offset 0x100, IO size 8 */
bank-width = <2>;
reg-shift = <1>;
reg-io-width = <1>;
interrupt-parent = <&gpio0>;
interrupts = <9 8>; /* gpio102 */
clock-frequency = <1843200>;
current-speed = <115200>;
};
uart@3,2 {
compatible = "ns16550a";
reg = <3 0x10 8>; /* CS3, offset 0x200, IO size 8 */
bank-width = <2>;
reg-shift = <1>;
reg-io-width = <1>;
interrupt-parent = <&gpio0>;
interrupts = <10 8>; /* gpio102 */
clock-frequency = <1843200>;
current-speed = <115200>;
};
uart@3,3 {
compatible = "ns16550a";
reg = <3 0x18 8>; /* CS3, offset 0x300, IO size 8 */
bank-width = <2>;
reg-shift = <1>;
reg-io-width = <1>;
interrupt-parent = <&gpio0>;
interrupts = <11 8>; /* gpio102 */
clock-frequency = <1843200>;
current-speed = <115200>;
};
ethernet@2,0 {
compatible = "davicom,dm9000";
reg = <2 0x08 2
2 0x400028 2>;
bank-width = <2>;
interrupt-parent = <&gpio2>;
interrupts = <23 2>; /* gpio158 */
local-mac-address = [00 00 00 00 00 00];
davicom,no-eeprom;
gpmc,mux-add-data = <0>;
gpmc,device-width = <1>;
gpmc,wait-pin = <0>;
gpmc,cycle2cycle-samecsen = <1>;
gpmc,cycle2cycle-diffcsen = <1>;
gpmc,cs-on-ns = <6>;
gpmc,cs-rd-off-ns = <180>;
gpmc,cs-wr-off-ns = <180>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <18>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
gpmc,we-on-ns = <54>;
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <144>;
gpmc,page-burst-access-ns = <24>;
gpmc,bus-turnaround-ns = <90>;
gpmc,cycle2cycle-delay-ns = <90>;
gpmc,wait-monitoring-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
gpmc,wr-access-ns = <0>;
};
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&nandflash_pins_default>;
pinctrl-1 = <&nandflash_pins_sleep>;
ranges = <0 0 0x08000000 0x2000000>,/* CS0: NAND */
<2 0 0x10000000 0x1000000>,/* CS2: DUART */
<3 0 0x11000000 0x1000000>;/* CS3: DUART */
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "rootfs";
reg = <0x00000000 0x20000000>;
};
};
uart@3,0 {
compatible = "ns16550a";
reg = <3 0 8>; /* CS3, offset 0, IO size 8 */
bank-width = <2>;
reg-shift = <1>;
reg-io-width = <1>;
interrupt-parent = <&gpio0>;
interrupts = <8 8>; /* gpio102 */
clock-frequency = <1843200>;
current-speed = <115200>;
gpmc,mux-add-data = <0>;
gpmc,device-width = <1>;
gpmc,wait-pin = <1>;
gpmc,cycle2cycle-samecsen = <1>;
gpmc,cycle2cycle-diffcsen = <1>;
gpmc,cs-on-ns = <5>;
gpmc,cs-rd-off-ns = <155>;
gpmc,cs-wr-off-ns = <155>;
gpmc,adv-on-ns = <15>;
gpmc,adv-rd-off-ns = <40>;
gpmc,adv-wr-off-ns = <40>;
gpmc,oe-on-ns = <45>;
gpmc,oe-off-ns = <145>;
gpmc,we-on-ns = <45>;
gpmc,we-off-ns = <145>;
gpmc,rd-cycle-ns = <155>;
gpmc,wr-cycle-ns = <155>;
gpmc,access-ns = <145>;
gpmc,page-burst-access-ns = <20>;
gpmc,bus-turnaround-ns = <20>;
gpmc,cycle2cycle-delay-ns = <20>;
gpmc,wait-monitoring-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-data-mux-bus-ns = <45>;
gpmc,wr-access-ns = <145>;
};
uart@3,1 {
compatible = "ns16550a";
reg = <3 0x8 8>; /* CS3, offset 0x100, IO size 8 */
bank-width = <2>;
reg-shift = <1>;
reg-io-width = <1>;
interrupt-parent = <&gpio0>;
interrupts = <9 8>; /* gpio102 */
clock-frequency = <1843200>;
current-speed = <115200>;
};
uart@3,2 {
compatible = "ns16550a";
reg = <3 0x10 8>; /* CS3, offset 0x200, IO size 8 */
bank-width = <2>;
reg-shift = <1>;
reg-io-width = <1>;
interrupt-parent = <&gpio0>;
interrupts = <10 8>; /* gpio102 */
clock-frequency = <1843200>;
current-speed = <115200>;
};
uart@3,3 {
compatible = "ns16550a";
reg = <3 0x18 8>; /* CS3, offset 0x300, IO size 8 */
bank-width = <2>;
reg-shift = <1>;
reg-io-width = <1>;
interrupt-parent = <&gpio0>;
interrupts = <11 8>; /* gpio102 */
clock-frequency = <1843200>;
current-speed = <115200>;
};
ethernet@2,0 {
compatible = "davicom,dm9000";
reg = <2 0x08 2
2 0x400028 2>;
bank-width = <2>;
interrupt-parent = <&gpio2>;
interrupts = <23 2>; /* gpio158 */
local-mac-address = [00 00 00 00 00 00];
davicom,no-eeprom;
gpmc,mux-add-data = <0>;
gpmc,device-width = <1>;
gpmc,wait-pin = <0>;
gpmc,cycle2cycle-samecsen = <1>;
gpmc,cycle2cycle-diffcsen = <1>;
gpmc,cs-on-ns = <6>;
gpmc,cs-rd-off-ns = <180>;
gpmc,cs-wr-off-ns = <180>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <18>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
gpmc,we-on-ns = <54>;
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <144>;
gpmc,page-burst-access-ns = <24>;
gpmc,bus-turnaround-ns = <90>;
gpmc,cycle2cycle-delay-ns = <90>;
gpmc,wait-monitoring-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
gpmc,wr-access-ns = <0>;
};
};
本dts主要是对am335x 的gpmc 外扩 nand 串口16554 网口dm9000 进行配置。
希望对做335x开发的朋友有所帮助。
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