Verilog

一. 门级结构描述

D触发器

module dflop(q,qb,clear,data,clk);     input clear,data,clk;     output q,qb;         not U5(net4,data);        nand U1(net1,clear,data,clk);        nand U6(net5,net4,clk);            nand U2(net2,net1,net6);        nand U7(net6,clear,net5,net2);             not U10(net8,clk);             nand U3(net3,net2,net8);        nand U8(net7,net6,net8);         nand U4(q,net3,qb);        nand U9(qb,net7,clear,q);     endmodule

四位移位寄存器

module SHIFT_REGI(q,qb,clear,data,clk);     input data, clear, clk;                   output [3:0]q, qb;                                                    dflop f3(q[3],qb[3],clear,data,clk),                           f2(q[2],qb[2],clear,q[3],clk),                        f1(q[1],qb[1],clear,q[2],clk),                  f0(q[0],qb[0],clear,q[1],clk); endmodule 

四位移位寄存器测试文件

`timescale 10ns/10ns module SHIFT_REGI_testbench;      reg clk,clear,data;       wire [3:0] q,qb;   initial       begin          clk = 0;           clear = 0;           data=0;           #40  clear = 1;           #200 clear = 0;           #100 $stop;       end   always #5 clk = ~clk;   always @(posedge clk)       data={$random}%2;   SHIFT_REGI m1(q,qb,clear,data,clk);   endmodule

二. 行为描述
四位计数器

module counter_4bits(Q,CLR,CLK);    input CLR,CLK;    output reg[3:0]Q;    always@(negedge CLK)      begin        if(CLR)           Q<=4'b0000;        else          Q<=Q+4'b0001;      endendmodule

测试文件

`timescale 10ns/10nsmodule counter_4Bits_testbench;    reg CLR,CLK;    wire [3:0] Q;initial    $monitor($time, "Count Q = %b Clear=%b",Q[3:0],CLR); initial    begin      CLK = 1'b0;      forever #5 CLK=~CLK;     endinitial    begin      CLR = 1'b1;      #10  CLR = 1'b0;       #200 CLR = 1'b1;       #30  $stop;    endcounter_4bits C1(Q,CLR,CLK);endmodule

模十计数器（模）

module couter_mo10(Q,CLR,CTR,CLK);    input CLR,CTR,CLK;    output reg[7:0]Q;always@(negedge CLK,negedge CLR)    begin      if(!CLR)         Q<=8'b0;      else if(CTR)      begin        if(Q[3:0]>=4'b1001)          begin            Q[3:0]<=4'b0;            Q[7:4]<=Q[7:4]+4'b0001;            if(Q[7:4]>=4'b1001)              Q<=8'b0;          end        else           Q[3:0]<=Q[3:0]+1;      end      else Q<=Q;    endendmodule

测试文件

`timescale 10ns/10nsmodule couter_mo10_testbench;    reg CLR,CTR,CLK;    wire [7:0] Q;initial    $monitor($time, "Count Q = %b Clear=%b en=%b",Q[7:0],CLR,CTR); initial    begin      CLK = 1'b0;      forever #5 CLK=~CLK;     endinitial    begin      CLR = 1'b0;      #10   CLR = 1'b1;       #1100 CLR = 1'b0;       #30   $stop;    endinitial    begin      CTR = 1'b0;      #10   CTR = 1'b1;       #1100 CTR = 1'b0;       #30   $stop;    endcouter_mo10 C1(Q,CLR,CTR,CLK);endmodule

优先编码器

module bianma_8bits(en,in7,in6,in5,in4,in3,in2,in1,in0,out );    input en,in7,in6,in5,in4,in3,in2,in1,in0;    output reg[2:0]out;                 always@(en,in7,in6,in5,in4,in3,in2,in1,in0)    begin      if(en)        begin          casex(in0) 1'b1:out=111;endcase          casex(in1) 1'b1:out=110;endcase           casex(in2) 1'b1:out=101;endcase          casex(in3) 1'b1:out=100;endcase          casex(in4) 1'b1:out=011;endcase           casex(in5) 1'b1:out=010;endcase          casex(in6) 1'b1:out=001;endcase          casex(in7) 1'b1:out=000;endcase        end      else out=3'bz;    endendmodule      

优先编码测试文件

`timescale 10ns/10nsmodule bianma_8bits_testbench;    reg en,in7,in6,in5,in4,in3,in2,in1,in0;    reg clk;    wire [2:0]out;initial    begin    $monitor($time, "en= %b in7= %b in6= %b in5= %b in4= %b in3= %b in2= %b in1= %b in0= %b out= %b" ,en,in7,in6,in5,in4,in3,in2,in1,in0,out);    en=1'b0;    clk= 1'b0;    #10 en=1'b1;    #300 en=1'b0;    #10 $stop;    endalways #5 clk=!clk;always @(posedge clk)    begin      in7 = {$random}%2;      in6 = {$random}%2;      in5 = {$random}%2;      in4 = {$random}%2;      in3 = {$random}%2;      in2 = {$random}%2;      in1 = {$random}%2;      in0 = {$random}%2;    endbianma_8bits bianma(en,in7,in6,in5,in4,in3,in2,in1,in0,out );endmodule  

module counter_super(a,clr,set,en,sel,clk,b,cout);    input wire [3:0]a;    input wire clr,set,en,sel,clk;    output reg [3:0]b;    output reg cout;always@(posedge clk)    begin      if(!clr)  begin        b <= 4'b0000; cout <= 1'b0; end        else          begin          if(set)  begin            b <= a; cout <= 1'b0; end          else               begin              if(!en)  begin                b <= b; cout <= cout; end              else                 begin                  case(sel)                     1'b1 : b <= b+1'b1;                     1'b0 : b <= b-1'b1; endcase                  if(sel == 1'b1) begin                    case(b) 4'b1111 : cout <= cout+1'b1;                             default cout <= cout; endcase  end                  if(sel == 1'b0) begin                     case(b) 4'b0000 : cout <= cout+1'b1;                             default cout <= cout; endcase  end                end               end        end     endendmodule

测试文件

`timescale 10ns/10nsmodule counter_super_testbench;    reg  [3:0]a;    reg  clr,set,en,sel,clk;    wire [3:0]b;    wire cout;initial    begin      $monitor($time, "a=%b clr=%b set=%b en=%b sel=%b clk=%b b=%b cout=%b", a,clr,set,en,sel,clk,b,cout);    endinitial    begin      a = 4'b0101;    endinitial    begin      clr = 0;          #10  clr = 1;      #100 clr = 0;      #10  $stop;    endinitial    begin          set = 1;      #10 set = 0;      #50 set = 1;      #5  set = 0;      #50 set = 1;      #10 $stop;    endinitial    begin          en = 0;      #15 en = 1;      #50 en = 0;      #5  en = 1;      #50 en = 0;      #10  $stop;endinitial    begin         sel = 0;     #60 sel = 1;     #50 sel = 0;     #10 $stop;    endinitial    begin      clk= 0;      forever #1 clk=!clk;    endcounter_super cs(a,clr,set,en,sel,clk,b,cout);endmodule

分频器

module fenpin(clk, ret, cout, clkx);    input clk, ret;    output reg [4:0]cout;    output reg clkx;always@(posedge clk)    begin      if(!ret)                                     begin          clkx = 0; cout = 0;        end      else                                     begin          cout = cout + 1'b1;          if(cout < 5'b01100) clkx = 0;            else if(cout < 5'b10110) clkx = 1;          else            cout = 0;                   end    endendmodule

曼彻斯特编码

module manche(clk, data, ret, dout);    input wire clk, data, ret;    output  dout;    reg f = 1;                    reg [1:0]zhuanhuan; always@(posedge clk)    begin      if(f == 1)       begin      if(!ret)                    zhuanhuan = 0;      else         begin          if(!data)            begin              zhuanhuan = 2'b01;            end          else            begin              zhuanhuan = 2'b10;            end        end      end    endalways@(posedge clk)    f = ~f;       assign dout = (f==0)?zhuanhuan[1]:zhuanhuan[0];endmodule

状态机（检测序列）

module zhuangtai(mark,data,clk,reset);  input data;  input clk,reset;  output  mark;  reg [7:0]state;  parameter IDLE = 4'd0,                          A    = 4'd1,                         B    = 4'd2,                         C    = 4'd3,                         D    = 4'd4,                         E    = 4'd5,                         F    = 4'd6,                         G    = 4'd7,            H    = 4'd8;  assign mark = (state==G)?1:0;  always@(posedge clk)  begin  if(!reset)    state<=IDLE;   else     begin      casex(state)               IDLE: if(data==1)                           state<=A;                           else state<=IDLE;                     A: if(data==1)                           state<=B;                           else state<=IDLE;                     B: if(data==0)                           state<=C;                           else state<=IDLE;                     C: if(data==0)                           state<=D;             else state<=IDLE;                     D: if(data==0)                           state<=E;                           else state<=IDLE;                      E: if(data==0)                           state<=F;                           else state<=IDLE;                     F: if(data==1)                           state<=G;                           else state<=IDLE;                     G: if(data==1)                           state<=H;                           else state<=IDLE;                    default: state<=IDLE;              endcase     end  endendmodulemodule ZT(mark,data,clk,reset);    input [7:0]data;    input clk,reset;    output reg mark;    reg [7:0]state = 8'b11000011;always@(posedge clk)    begin      if(!reset)        mark = 0;      else       begin      if(  data[0]==state[0]         &&data[1]==state[1]              &&data[2]==state[2]         &&data[3]==state[3]         &&data[4]==state[4]         &&data[5]==state[5]         &&data[6]==state[6]         &&data[7]==state[7]) mark = 1;       else mark = 0;      end    endendmodule