Arm power information

The shared L3 cache simplifies process migration between the cores.

The Snoop Control Unit (SCU) maintains coherency between caches in the cores and L3.

The SCU includes a Snoop Filter to optimize coherency maintenance operations.

ETM：Each core includes an Embedded Trace Macrocell (ETM 嵌入式跟踪宏单元) to allow program tracing while debugging.

ACP: Accelerator Coherency Port (provides direct memory access to cacheable areas of main memory)

RAS: Reliability, Availability, and Serviceability

DFT: for logictesting (可测试性设计：Design for Testability)

MBIST: for ram testing(存储器内建自测试：Memory Build-in self-test)

TRM: Technical Reference Manual 技术参考手册

Core[0] Core[CN] :CN represents a set of cores, where CN has avalue of the total number of cores -1.

A ProcessingElement (PE) performs a thread of execution.

A single-threaded core has one PE and a multi-threaded core has two or more PEs.

Power management:

The cluster supports a set of power-saving modes that are controlled by an external powercontroller.

The modes areselected through power-mode requests on P-channels for each cores and a separate P-Channel for

the common cluster control logic.

1)   nCPUPORESET[CN:0]: primary powerup reset signal for all resettable registers in the coreclk domain includingdebug registers,

                   ETM registers, and RASregisters. (per-core) (最初的上电复位)

2)   nCORERESET[CN:0]:Warm reset signal for all resettable registersin the coreclk domainexcluding the debugregisters….. （热启动，low power中用）

All reset inputs can be asserted (High to low) 低电平有效 and deasserted (low to high)

At Exception level 3 (EL3), cores can only transition between AArch32 and AArch64 states at reset.

The Execution state after reset is controlled by the AA64nAA32[PE:0] configuration signals. These signals areonly sampled at reset.

The FCM cluster,in conjunction with power management software, giving operating requirements hints (操作要求提示) to an external power

Controller. The power controller is responsible for coordinating(协调) power management with the rest of the soc, switching and isolating power and 

voltage domains, and controlling clock gating cells.

The operating requirements indicate:

the required cache capacity, the RAM retention mode and whether the cluster logic can be powered up or down.

来自谷歌

Some computers provide several sleep modes. In the ‘light’ sleep mode, the CPU simplystops executing instructions.

In a ‘heavy’ sleep mode, the CPU not only stops executing instructions, but also takes other steps that reduce its power consumption.

e.g slowing/gating clocks and disconnecting the CPU from the system bus. Ideally, the kernel shouldput the CPU into the deepest sleep

mode possible whenthe system does not have processes in the readystate(在就绪状态).

However, a CPU takes a longer time to ‘wake up’ from a heavy sleep mode than it would from alight sleep mode, so the kernel has to

Make a trade-off here. It starts by putting the CPU in the light sleep mode. If no processesbecome ready for some time, it puts the CPU

Into a heavier sleep mode, and so on. This way, it conserves(保存) only as much power as possible without sacrificing response times

So much.

Operating systemslike Unix and Windows have generalized power management to include all devices.

Typically, a deviceis put into a lower power consuming state if it has been dormant(休眠的，静止的) as its present power consuming

State for sometime.