BUSES AND CONTROLLERS

The first two I/O taskes noted in section 1.4 concren the establishment of connections between the memory and the I/O devices and the controll of data transfers over this connection.Most modern conputers use a bus,or buses, for interconnecting the major conponents of the system.A bus serves as a pathway between conponents for passing address, instructions, and data. A simple high-level view of a bus is shown is fig1-13.This is the bus shown in fig 1- 12 that is used with the processor I/O. This bus interconnects the processor,main memory,and I/O devices by mean of their controllers.Buses can be classified in a number of ways:by purpose, control,and communication techniqueI/O的前两个任务是在存储器和I/o设备之间建立连接并在这中连接上控制数据的传输，大多数现在的计算机用一条或者多条总线连接系统的各个主要部件，总线的作用是为各个部件传送地址，指令，数据提供通路，图 1-13位主线的高层次简单视图，这是图1-12 中用于协处理器I/O的总线，这一总线有控制器将处理器，主存储器和I/O设备连在一起。总线可以按照多种方式分类：既按目的的，按照控制方法和按照通讯技术分类

1.Dedicated or general purpose
专用或者通用
The major difference between dedicated and general_purpose buses is that a dedicated bus is point-to-point between two physical devices,whereas a general-purpose bus interconnects more than two physical devices.fig 1-14 illustrates the two types. Dedicated buses are used in cases in which the latency and the bandwidth requirements are sunch that sharing the bus with another user can result in unacceptable system performance. Note that a dedicated buses are unidirectional with information flow in only one direction. for example, the bus that connects a memory to a graphics controller may be unidirecional.
专用和通用总线的主要区分为：专用总线在两个物理设备之间的点对点的链接，而通用总线连接多于两个物理设备，图1-14展示了两种连接类型，当与另一用户共享总线时，如果由于等待时间和贷款要求得不到满足使系统性能下降到不能忍受时，需采用专用总线，注意，由于在专用总线中，源和目的的地址是隐含的，所以不需要地址线，也就是设备1总是向设备2发送信号和相反，某些专用总线是单向的，信号流通是一个方向，例如连接存储器和图形控制器的总线可以是单向的。

Because dedicates buses are used internal to the processor or for special high-bandwidth applications without general purpose capabilities, these buses are not condidered further.Instead, the following paragraphs discuss the control and communications design techniques found with general-purpose buses.由于专用总线用于处理器内部，或由于不需要通用功能的大宽带专用系统，因而这些总线不做进一步讨论，相反，下面将讨论通用总线中的控制和通信设计技术，Also, with a general-purpose bus, a number of users share the same bus and simulataneous requests for the bus are resolved by one of a number of resolution techniques, Some of the devices on a general-puepose bus are both senders and receivers or only senders or only receivers. For example. A printer controller's primary function is to recieve data and send some status . A disk controller, on the other hand sends and receives data and send status information.同样，对于通用总线，多个用户共享同一总线，当他们同时对总线提出请求时，可采用多种技术中的一种加以解决，通用总线上的某个设备可以既是发送器有是接收器，也可以只发送和接受数据，又要发送状态信息。

2.Centralized or Decentralized control
集中式和分散式
The control of a general_purpose bus can be either centralized or decentralized. The basic requirement is to grant or not grant a device access to the bus , with centralized or decentralized control, all devices are treated equally except for the priority of access.Thus. if one of the devices is the processor. it may be given the highest priority becuse of the loss in system performance ; for example ,if a disk is unable to read and misses a complete revolution,many millionseconds will be lost;
通用总线的控制既可以是集中式也可以是分散式，其基本要求是授予或者不授予设备对总显得访问权限，处理访问总线的有限级外，集中式和分散式控制对待所有的设备都是一视同仁的，因此，如果设备是处理，则应给它以总线访问的最高优先级，但是在某些系统中，为了避免对系统性能的损害，要让某个I/O设备具有最高的优先级别，例如磁盘转一圈还读不出数据，则会损害更多的时间。
Centralized control. A single hardware control unit will recognize a request and grant access to the bus to a requesting device, It is the responsibility of the controller to resolve simulaneous requests and assign priority to the requests ,At last three designs are used for centralized controllers: daisy chain,polling with a global counter,and polling with local conters.
集中控制，用一个控制硬件去识别总线请求并允许请求设备去访问总线，该控制器的责任是处理同事来的多个请求并对这些请求安排优先级，集中控制器至少有3中方式，菊花链，轮询式，带局部计时器的轮询式。
Distributes control,Distributesd control，as known as decenrtrslized control,distributes the control function between all the devices on the bus, the major advantage of decentralize control is that the system is easily expandable by the addation of modules,As with centralized control, there are three basic designs: daisy chain,polling, and independent requests.
分布式控制，分布式控制又称为分散式控制，他把控制功能分布在总线上的所有设备，分散式控制的主要优点是容易通过模块扩充功能，与集中控制一样，分散式控制也有三种模式，菊花链，轮询和独立请求。

3.Synchronous or asynchronous communication
同步或者异步通讯
The transmission of addresses,control information,and data between two devices may be synchronous with a block, or asynchronous with a clock and self-timed.
地址，控制信息和数据在两个设备之间可以用一个时钟同步传送或不用时钟，而用自身定时器实现异步传送，
Synchronous communication, A simplified diagram of a synchronous bus (the data and clock portion) connected between two devices is shown on the left of fig 1-15 data are to be transmitted between the card in the right-hand slot to the card in the left-hand slot, the transmitter and the receiver are locked from a common source on the left-hand card
同步通讯，连接两个设备的同步总线（数据和时钟部分）简化矿体1-15所示，数据从右边槽中的卡传到左边槽中的卡。发送器和接收器用左边卡上的公共时钟源同步。

Asynchronous communication. Asynchronous communication for buses was developed to overcome the worest-case clock rate limitations of synchronous systems, With Synchronous communications data tranfers occur at the fastest rate and smallesr delay possible under the circumstances of the physical status of the bus.As cards are added to the bus. the timing automatically abjusts for rach cards. there are a number of asynchronous protocools,however, only one of the simpler ones is discussed here.异步通讯，总线异步是为了克服同步系统中很差的时钟频率限制开发的，异步通讯中数据在总线的实际状态环境下以最快的速度和最小的延时传送，当一些卡到总线上时，会自动为每一个卡调整时钟，异步通讯协议有很多种。这里只讨论最简单的一种。The timing dialram for an asynchronous exchange is shown in fig 1-16.the figure illustrates are the action when a source send data to a destination.发送方向和接收方向上接收数据时的工作过程。

4.Bus design example
总线设计举例
PCI
The peripheral component interconnect(PCI) is a recent high-handwidth, processor-independt bus that can function as a mezzanine or peripheral bus.compared with other comman bus specifications,PCI delivers better system performance for high-speed I/O subsystem.the current standard allows the use of up to 64date lines at 33Mhz, for a raw tranfer rate of 264Mb/s or 2.112Gb/s. but it is not just a high speed that makes PCI attractive.Encomically, PCI is specially designed to meet the I/O requirement of modern system. it requires very few chip to implement and suports other buses attached to the PCI bus.
外部部件互连PCI是一种进来使用的大带宽，独立于处理器的总线，可以用作底层或外围总线，与其他通用总线规范比较，PCI为高速I/O子系统，提供更好的系统性能，现在标准是在33Mhz，可以使用最多达64条数据线，和源数据传输速率可达到264Mb/s或者2.112Gb/s PCI不仅因高速传送速率而具有吸引力，他还满足低价位的现代系统而专门设计的，只要很少的芯片饥渴实现与PCI总线连接的其他类型总线，
PCI is designed to support a variety of microprocessor-based configurations.including both single-and multiple-processor systems,Accordingly, it provides a general-purpose set of functions.It makes use of synchronous timing and a centralized arbition schema.
PCI支持各种基于微处理器的配置，包括单处理器设备和多处理器设备，相应的，他提供一套通用的功能，并采用同步定时和集中仲裁机制。
A combined DRAM controller and bridge to the PCI bus provides tight coupling with processor and the ability to deliver data at high speeds . The bridge acts as a data buffer so that the speed of th PCI bus may differ from that of the processor’s I/O capability,in a multiprocessor system, one or more PCI configurations may be connected by bridge to the processor’s system bus.the system bus supports only the processor/cache units, main memory,and the　pci bridges, Again ,the use of bridges keeps the PCI independt of the processor speed yet provides the ability to receive and deliver data rapily.
连向PCI总线的DRAM控制器和桥接器的组合与处理器紧密耦合，具有高速数据传送能力，桥接器的作用在于数据缓冲器，用于解决PCI总线速度与处理器I/O能力不匹配的问题，在多处理器系统中可通过桥接器把一个或者多个PCI配置与处理器系统总线相连，系统总线只支持处理器器-高速缓存部件，主存储器和pCI桥接器，再者，桥接器的使用让PCI与处理器的速度无关，却带来了数据接收和传送的高速度。

Keywords:
bus 总线
synchronous 同步
asynchronous 异步
decentralized 分散式
distributed 分布式
priority 优先级
daisy chain 菊花链
polling轮询
peripheral compnont interconnect 外围部件互连
adapter 适配器
timing 定时 同步
dedicated bus 专用总线
general-purpose bus 通用总线
share 共享
bandwidth 带宽