三、SCM 数码管&FPGA 数码管

（未完待续）

module  div_smg(sm_cs1,clk,rst_n,sw,smg);/*  共阴极 :不带小数点              ;0,  1,  2,  3,  4, 5,  6,  7,        db      3fh,06h,5bh,4fh,66h,6dh,7dh,07h               ;8,  9, a,  b,   c,  d,  e,  f , 灭         db      7fh,6fh,77h,7ch,39h,5eh,79h,71h,00h*/reg [7:0] seg[15:0];initialbegin         seg[0] = 7'h3f;            seg[1]  = 7'h06;            seg[2]  = 7'h5b;            seg[3]  = 7'h4f;            seg[4]  = 7'h66;            seg[5]  = 7'h6d;            seg[6]  = 7'h7d;            seg[7]  = 7'h07;            seg[8]  = 7'h7f;            seg[9]  = 7'h6f;            seg[10] = 7'h77;            seg[11] = 7'h7c;            seg[12] = 7'h39;            seg[13] = 7'h5e;            seg[14] = 7'h79;            seg[15] = 7'h71;endoutput sm_cs1;input clk;input rst_n;input sw;output reg [7:0] smg;reg clk_div_1;always@(posedge clk or negedge rst_n)if(!rst_n) clk_div_1<=1'b1;else clk_div_1<=sw;reg clk_div_2;always@(posedge clk or negedge rst_n)if(!rst_n) clk_div_2<=1'b1;else clk_div_2<=clk_div_1;wire key_an_1=(~clk_div_1)&(clk_div_2);reg [19:0] cnt;always@(posedge clk or negedge rst_n)if(!rst_n) cnt<=20'h0;else if(key_an_1) cnt<=20'h0;else cnt<=cnt+1'b1;reg clk_div_3;always@(posedge clk or negedge rst_n)if(!rst_n) clk_div_3<=1'b1;else if(cnt==20'hfffff) clk_div_3<=sw;reg clk_div_4;always@(posedge clk or negedge rst_n)if(!rst_n) clk_div_4<=1'b1;else clk_div_4<=clk_div_3;wire key_an_2=(~clk_div_3)&clk_div_4;reg [3:0] num;always@(posedge clk or negedge rst_n)if(!rst_n) beginnum<=1'b0;smg<=2'h00;endelse if(key_an_2==1) beginsmg<=seg[num];num<=num+1'b1;endassign sm_cs1=1'b0;endmodule