uboot源码解析

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Lds文件自己分析，我们不说了，看下uboot源码（和配置一个版本）

首先查看_start

22 .globl _start

23 _start: b reset

24 ldr pc, _undefined_instruction

25 ldr pc, _software_interrupt

26 ldr pc, _prefetch_abort

27 ldr pc, _data_abort

28 ldr pc, _not_used

29 ldr pc, _irq

30 ldr pc, _fiq

然后看下reset

94 reset:

95 bl save_boot_params

96 /*

97 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,

98 * except if in HYP mode already

99 */

//设置svc模式，并且屏蔽irq和fiq

100 mrs r0, cpsr //保存cpsr的值

101 and r1, r0, #0x1f @ mask mode bits //只取cpsr的最后5位

102 teq r1, #0x1a @ test for HYP mode

103 bicne r0, r0, #0x1f @ clear all mode bits

104 orrne r0, r0, #0x13 @ set SVC mode

105 orr r0, r0, #0xc0 @ disable FIQ and IRQ

106 msr cpsr,r0

107

108 /*

109 * Setup vector:

110 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.

111 * Continue to use ROM code vector only in OMAP4 spl)

112 */

// ./include/configs/ti_omap4_common.h:#define CONFIG_OMAP44XX

// am33xx_evm.h文件中定义了#ifndef CONFIG_SPL_BUILD

113 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))

114 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */

115 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register

116 bic r0, #CR_V @ V = 0

117 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register

118

119 /* Set vector address in CP15 VBAR register */

120 ldr r0, =_start

121 mcr p15, 0, r0, c12, c0, 0 @Set VBAR

122 #endif

123

124 /* the mask ROM code should have PLL and others stable */

125 #ifndef CONFIG_SKIP_LOWLEVEL_INIT

126 bl cpu_init_cp15 //主要是关闭cache和mmu

127 bl cpu_init_crit //

128 #endif

129

130 bl _main

逐条分析：

163 ENTRY(save_boot_params)

164 bx lr @ back to my caller

所以是空

cpsr（状态寄存器）

协处理器没研究过，以后再查看；

243 ENTRY(cpu_init_crit)

244 /*

245 * Jump to board specific initialization...

246 * The Mask ROM will have already initialized

247 * basic memory. Go here to bump up clock rate and handle

248 * wake up conditions.

249 */

250 b lowlevel_init @ go setup pll,mux,memory

251 ENDPROC(cpu_init_crit)

看一下lowlevel_init

18 ENTRY(lowlevel_init)

19 /*

20 * Setup a temporary stack

21 */

22 ldr sp, =CONFIG_SYS_INIT_SP_ADDR

23 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ //8字节对齐

24 #ifdef CONFIG_SPL_BUILD //我们定义了

25 ldr r9, =gdata

26 #else

27 sub sp, sp, #GD_SIZE

28 bic sp, sp, #7

29 mov r9, sp

30 #endif

31 /*

32 * Save the old lr(passed in ip) and the current lr to stack

33 */

34 push {ip, lr} //将以前的lr（返回地址）存储在现在的栈上

36 /*

37 * go setup pll, mux, memory

38 */

39 bl s_init

40 pop {ip, pc} //pc=lr

41 ENDPROC(lowlevel_init)

CONFIG_SYS_INIT_SP_ADDR="(NON_SECURE_SRAM_END - GENERATED_GBL_DATA_SIZE)"

#define NON_SECURE_SRAM_END 0x40310000

#define GENERATED_GBL_DATA_SIZE 192

205 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) //我们定义的是第一个

206 void s_init(void)

207 {

208 /*

209 * The ROM will only have set up sufficient pinmux to allow for the

210 * first 4KiB NOR to be read, we must finish doing what we know of

211 * the NOR mux in this space in order to continue.

212 */

213 #ifdef CONFIG_NOR_BOOT

214 enable_norboot_pin_mux();

215 #endif

216 /*

217 * Save the boot parameters passed from romcode.

218 * We cannot delay the saving further than this,

219 * to prevent overwrites.

220 */

221 #ifdef CONFIG_SPL_BUILD

222 save_omap_boot_params();

223 #endif

224 watchdog_disable();

225 timer_init();

226 set_uart_mux_conf();

227 setup_clocks_for_console();

228 uart_soft_reset();

229 #ifdef CONFIG_NOR_BOOT

230 gd->baudrate = CONFIG_BAUDRATE;

231 serial_init();

232 gd->have_console = 1;

233 #elif defined(CONFIG_SPL_BUILD)

234 gd = &gdata;

235 preloader_console_init();

236 #endif

237 prcm_init();

238 set_mux_conf_regs();

239 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)

240 /* Enable RTC32K clock */

241 rtc32k_enable();

242 #endif

243 sdram_init();

244 }

245 #endif

进行各种初始化；

下面看一下_main(arch/arm/lib/crt0.S)

54 /*

55 * entry point of crt0 sequence

56 */

58 ENTRY(_main)

60 /*

61 * Set up initial C runtime environment and call board_init_f(0).

62 */

64 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)

65 ldr sp, =(CONFIG_SPL_STACK)

66 #else

67 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)

68 #endif

//给gd分配空间，然后初始化

69 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */

70 sub sp, sp, #GD_SIZE /* allocate one GD above SP */

71 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */

72 mov r9, sp /* GD is above SP */

73 mov r0, #0

74 bl board_init_f //初始化

76 #if ! defined(CONFIG_SPL_BUILD)

78 /*

79 * Set up intermediate environment (new sp and gd) and call

80 * relocate_code(addr_moni). Trick here is that we'll return

81 * 'here' but relocated.

82 */

84 ldr sp, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */

85 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */

86 ldr r9, [r9, #GD_BD] /* r9 = gd->bd */

87 sub r9, r9, #GD_SIZE /* new GD is below bd */

89 adr lr, here

90 ldr r0, [r9, #GD_RELOC_OFF] /* r0 = gd->reloc_off */

91 add lr, lr, r0

92 ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */

93 b relocate_code

94 here:

96 /* Set up final (full) environment */

98 bl c_runtime_cpu_setup /* we still call old routine here */

100 ldr r0, =__bss_start /* this is auto-relocated! */

101 ldr r1, =__bss_end /* this is auto-relocated! */

102

103 mov r2, #0x00000000 /* prepare zero to clear BSS */

104

105 clbss_l:cmp r0, r1 /* while not at end of BSS */

106 strlo r2, [r0] /* clear 32-bit BSS word */

107 addlo r0, r0, #4 /* move to next */

108 blo clbss_l

109

110 bl coloured_LED_init

111 bl red_led_on

112

113 /* call board_init_r(gd_t *id, ulong dest_addr) */

114 mov r0, r9 /* gd_t */

115 ldr r1, [r9, #GD_RELOCADDR] /* dest_addr */

116 /* call board_init_r */

117 ldr pc, =board_init_r /* this is auto-relocated! */

118

119 /* we should not return here. */

120

121 #endif

122

123 ENDPROC(_main)

最后有一个board_init_r，里面有main_loop死循环，用于接收命令，或者启动系统，以后再说。

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