4（2）、uboot中内存初始化函数：mem_ctrl_asm_init

#include <config.h>#include <s5pc110.h>.globl mem_ctrl_asm_initmem_ctrl_asm_init:#ifndef CONFIG_EVT1ldr     r0, =ASYNC_MSYS_DMC0_BASEldr     r1, =0x0str     r1, [r0, #0x0]/* This register is removed at EVT1 of C110. */ldr     r1, =0x0str     r1, [r0, #0xC]#endif#ifdef CONFIG_MCP_SINGLE/* DMC0 Drive Strength (Setting 2X) */ldrr0, =ELFIN_GPIO_BASEldrr1, =0x0000AAAAstrr1, [r0, #MP1_0DRV_SR_OFFSET]ldrr1, =0x0000AAAAstrr1, [r0, #MP1_1DRV_SR_OFFSET]ldrr1, =0x0000AAAAstrr1, [r0, #MP1_2DRV_SR_OFFSET]ldrr1, =0x0000AAAAstrr1, [r0, #MP1_3DRV_SR_OFFSET]ldrr1, =0x0000AAAAstrr1, [r0, #MP1_4DRV_SR_OFFSET]ldrr1, =0x0000AAAAstrr1, [r0, #MP1_5DRV_SR_OFFSET]ldrr1, =0x0000AAAAstrr1, [r0, #MP1_6DRV_SR_OFFSET]ldrr1, =0x0000AAAAstrr1, [r0, #MP1_7DRV_SR_OFFSET]ldrr1, =0x00002AAAstrr1, [r0, #MP1_8DRV_SR_OFFSET]/* DMC1 Drive Strength (Setting 2X) */ldrr0, =ELFIN_GPIO_BASEldrr1, =0x0000AAAAstrr1, [r0, #MP2_0DRV_SR_OFFSET]ldrr1, =0x0000AAAAstrr1, [r0, #MP2_1DRV_SR_OFFSET]ldrr1, =0x0000AAAAstrr1, [r0, #MP2_2DRV_SR_OFFSET]ldrr1, =0x0000AAAAstrr1, [r0, #MP2_3DRV_SR_OFFSET]ldrr1, =0x0000AAAAstrr1, [r0, #MP2_4DRV_SR_OFFSET]ldrr1, =0x0000AAAAstrr1, [r0, #MP2_5DRV_SR_OFFSET]ldrr1, =0x0000AAAAstrr1, [r0, #MP2_6DRV_SR_OFFSET]ldrr1, =0x0000AAAAstrr1, [r0, #MP2_7DRV_SR_OFFSET]ldrr1, =0x00002AAAstrr1, [r0, #MP2_8DRV_SR_OFFSET]/* DMC0 initialization at single Type*/ldrr0, =APB_DMC_0_BASEldrr1, =0x00101000@PhyControl0 DLL parameter setting, manual 0x00101000strr1, [r0, #DMC_PHYCONTROL0]ldrr1, =0x00000086@PhyControl1 DLL parameter setting, LPDDR/LPDDR2 Casestrr1, [r0, #DMC_PHYCONTROL1]ldrr1, =0x00101002@PhyControl0 DLL onstrr1, [r0, #DMC_PHYCONTROL0]ldrr1, =0x00101003@PhyControl0 DLL startstrr1, [r0, #DMC_PHYCONTROL0]find_lock_val:ldrr1, [r0, #DMC_PHYSTATUS]@Load Phystatus register valueandr2, r1, #0x7cmpr2, #0x7@Loop until DLL is lockedbnefind_lock_valandr1, #0x3fc0 movr2, r1, LSL #18orrr2, r2, #0x100000orrr2 ,r2, #0x1000orrr1, r2, #0x3@Force Value lockingstrr1, [r0, #DMC_PHYCONTROL0]#if 0/* Memory margin test 10.01.05 */orrr1, r2, #0x1@DLL offstrr1, [r0, #DMC_PHYCONTROL0]#endif/* setting DDR2 */ldrr1, =0x0FFF2010@ConControl auto refresh offstrr1, [r0, #DMC_CONCONTROL]ldrr1, =DMC0_MEMCONTROL@MemControl BL=4, 1 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down offstrr1, [r0, #DMC_MEMCONTROL]ldrr1, =DMC0_MEMCONFIG_0@MemConfig0 256MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixedstrr1, [r0, #DMC_MEMCONFIG0]ldrr1, =DMC0_MEMCONFIG_1@MemConfig1strr1, [r0, #DMC_MEMCONFIG1]ldrr1, =0xFF000000@PrechConfigstrr1, [r0, #DMC_PRECHCONFIG]ldrr1, =DMC0_TIMINGA_REF@TimingAref7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4E)strr1, [r0, #DMC_TIMINGAREF]ldrr1, =DMC0_TIMING_ROW@TimingRowfor @200MHzstrr1, [r0, #DMC_TIMINGROW]ldrr1, =DMC0_TIMING_DATA@TimingDataCL=3strr1, [r0, #DMC_TIMINGDATA]ldrr1, =DMC0_TIMING_PWR@TimingPowerstrr1, [r0, #DMC_TIMINGPOWER]ldrr1, =0x07000000@DirectCmdchip0 Deselectstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x01000000@DirectCmdchip0 PALLstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00020000@DirectCmdchip0 EMRS2strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00030000@DirectCmdchip0 EMRS3strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00010400@DirectCmdchip0 EMRS1 (MEM DLL on, DQS# disable)strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00000542@DirectCmdchip0 MRS (MEM DLL reset) CL=4, BL=4strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x01000000@DirectCmdchip0 PALLstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x05000000@DirectCmdchip0 REFAstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x05000000@DirectCmdchip0 REFAstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00000442@DirectCmdchip0 MRS (MEM DLL unreset)strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00010780@DirectCmdchip0 EMRS1 (OCD default)strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00010400@DirectCmdchip0 EMRS1 (OCD exit)strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x07100000@DirectCmdchip1 Deselectstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x01100000@DirectCmdchip1 PALLstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00120000@DirectCmdchip1 EMRS2strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00130000@DirectCmdchip1 EMRS3strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00110400@DirectCmdchip1 EMRS1 (MEM DLL on, DQS# disable)strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00100542@DirectCmdchip1 MRS (MEM DLL reset) CL=4, BL=4strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x01100000@DirectCmdchip1 PALLstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x05100000@DirectCmdchip1 REFAstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x05100000@DirectCmdchip1 REFAstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00100442@DirectCmdchip1 MRS (MEM DLL unreset)strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00110780@DirectCmdchip1 EMRS1 (OCD default)strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00110400@DirectCmdchip1 EMRS1 (OCD exit)strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x0FF02030@ConControlauto refresh onstrr1, [r0, #DMC_CONCONTROL]ldrr1, =0xFFFF00FF@PwrdnConfigstrr1, [r0, #DMC_PWRDNCONFIG]ldrr1, =0x00202400@MemControlBL=4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down offstrr1, [r0, #DMC_MEMCONTROL]/* DMC1 initialization */ldrr0, =APB_DMC_1_BASEldrr1, =0x00101000@Phycontrol0 DLL parameter settingstrr1, [r0, #DMC_PHYCONTROL0]ldrr1, =0x00000086@Phycontrol1 DLL parameter settingstrr1, [r0, #DMC_PHYCONTROL1]ldrr1, =0x00101002@PhyControl0 DLL onstrr1, [r0, #DMC_PHYCONTROL0]ldrr1, =0x00101003@PhyControl0 DLL startstrr1, [r0, #DMC_PHYCONTROL0]find_lock_val1:ldrr1, [r0, #DMC_PHYSTATUS]@Load Phystatus register valueandr2, r1, #0x7cmpr2, #0x7@Loop until DLL is lockedbnefind_lock_val1andr1, #0x3fc0 movr2, r1, LSL #18orrr2, r2, #0x100000orrr2, r2, #0x1000orrr1, r2, #0x3@Force Value lockingstrr1, [r0, #DMC_PHYCONTROL0]#if 0/* Memory margin test 10.01.05 */orrr1, r2, #0x1@DLL offstrr1, [r0, #DMC_PHYCONTROL0]#endif/* settinf fot DDR2 */ldrr0, =APB_DMC_1_BASEldrr1, =0x0FFF2010@auto refresh offstrr1, [r0, #DMC_CONCONTROL]ldrr1, =DMC1_MEMCONTROL@MemControlBL=4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down offstrr1, [r0, #DMC_MEMCONTROL]ldrr1, =DMC1_MEMCONFIG_0@MemConfig0512MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixedstrr1, [r0, #DMC_MEMCONFIG0]ldrr1, =DMC1_MEMCONFIG_1@MemConfig1strr1, [r0, #DMC_MEMCONFIG1]ldrr1, =0xFF000000strr1, [r0, #DMC_PRECHCONFIG]ldrr1, =DMC1_TIMINGA_REF@TimingAref7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4strr1, [r0, #DMC_TIMINGAREF]ldrr1, =DMC1_TIMING_ROW@TimingRowfor @200MHzstrr1, [r0, #DMC_TIMINGROW]ldrr1, =DMC1_TIMING_DATA@TimingDataCL=3strr1, [r0, #DMC_TIMINGDATA]ldrr1, =DMC1_TIMING_PWR@TimingPowerstrr1, [r0, #DMC_TIMINGPOWER]ldrr1, =0x07000000@DirectCmdchip0 Deselectstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x01000000@DirectCmdchip0 PALLstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00020000@DirectCmdchip0 EMRS2strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00030000@DirectCmdchip0 EMRS3strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00010400@DirectCmdchip0 EMRS1 (MEM DLL on, DQS# disable)strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00000542@DirectCmdchip0 MRS (MEM DLL reset) CL=4, BL=4strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x01000000@DirectCmdchip0 PALLstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x05000000@DirectCmdchip0 REFAstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x05000000@DirectCmdchip0 REFAstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00000442@DirectCmdchip0 MRS (MEM DLL unreset)strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00010780@DirectCmdchip0 EMRS1 (OCD default)strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00010400@DirectCmdchip0 EMRS1 (OCD exit)strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x07100000@DirectCmdchip1 Deselectstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x01100000@DirectCmdchip1 PALLstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00120000@DirectCmdchip1 EMRS2strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00130000@DirectCmdchip1 EMRS3strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00110440@DirectCmdchip1 EMRS1 (MEM DLL on, DQS# disable)strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00100542@DirectCmdchip1 MRS (MEM DLL reset) CL=4, BL=4strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x01100000@DirectCmdchip1 PALLstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x05100000@DirectCmdchip1 REFAstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x05100000@DirectCmdchip1 REFAstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00100442@DirectCmdchip1 MRS (MEM DLL unreset)strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00110780@DirectCmdchip1 EMRS1 (OCD default)strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00110400@DirectCmdchip1 EMRS1 (OCD exit)strr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x0FF02030@ConControlauto refresh onstrr1, [r0, #DMC_CONCONTROL]ldrr1, =0xFFFF00FF@PwrdnConfigstrr1, [r0, #DMC_PWRDNCONFIG]ldrr1, =DMC1_MEMCONTROL@MemControlBL=4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down offstrr1, [r0, #DMC_MEMCONTROL]#else/* CONFIG_MCP_SINGLE *//* DMC0 initialization */ldrr0, =APB_DMC_0_BASEldrr1, =0x00101000@Phycontrol0 DLL parameter settingstrr1, [r0, #DMC_PHYCONTROL0]ldrr1, =0x00000084@Phycontrol1 DLL parameter settingstrr1, [r0, #DMC_PHYCONTROL1]ldrr1, =0x00101002@Phycontrol2 DLL parameter settingstrr1, [r0, #DMC_PHYCONTROL0]ldrr1, =0x00101003@Dll onstrr1, [r0, #DMC_PHYCONTROL0]find_lock_val:ldrr1, [r0, #DMC_PHYSTATUS]@Load Phystatus register valueand r2, r1, #0x7cmpr2, #0x7@Loop until DLL is lockedbnefind_lock_valandr1, #0x3fc0 movr2, r1, LSL #18orrr2, r2, #0x100000orrr2, r2, #0x1000orrr1, r2, #0x3@Force Value lockingstrr1, [r0, #DMC_PHYCONTROL0]#if 1 /* DRAM margin test 10.01.06 */orrr1, r2, #0x1@DLL offstrr1, [r0, #DMC_PHYCONTROL0]#endifldrr1, =0x0fff1010@auto refresh offstrr1, [r0, #DMC_CONCONTROL]ldrr1, =0x00212100strr1, [r0, #DMC_MEMCONTROL]ldrr1, =DMC0_MEMCONFIG_0strr1, [r0, #DMC_MEMCONFIG0]ldrr1, =DMC0_MEMCONFIG_1strr1, [r0, #DMC_MEMCONFIG1]ldrr1, =0xff000000strr1, [r0, #DMC_PRECHCONFIG]ldrr1, =DMC0_TIMINGA_REFstrr1, [r0, #DMC_TIMINGAREF]ldrr1, =DMC0_TIMING_ROW@TimingRow@133MHzstrr1, [r0, #DMC_TIMINGROW]ldrr1, =DMC0_TIMING_DATAstrr1, [r0, #DMC_TIMINGDATA]ldrr1, =DMC0_TIMING_PWR@Timing Powerstrr1, [r0, #DMC_TIMINGPOWER]ldrr1, =0x07000000@chip0 Deselectstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x01000000@chip0 PALLstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x05000000@chip0 REFAstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x05000000@chip0 REFAstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00000032@chip0 MRSstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x07100000@chip1 Deselectstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x01100000@chip1 PALLstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x05100000@chip1 REFAstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x05100000@chip1 REFAstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00100032@chip1 MRSstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x0FFF20B0@ConControl auto refresh onstrr1, [r0, #DMC_CONCONTROL]ldrr1, =0xFFFF00FF@PwrdnConfigstrr1, [r0, #DMC_PWRDNCONFIG]ldrr1, =0x00212113@MemControlstrr1, [r0, #DMC_MEMCONTROL]/* DMC1 initialization */ldrr0, =APB_DMC_1_BASEldrr1, =0x00101000@Phycontrol0 DLL parameter settingstrr1, [r0, #DMC_PHYCONTROL0]ldrr1, =0x00000084@Phycontrol1 DLL parameter settingstrr1, [r0, #DMC_PHYCONTROL1]ldrr1, =0x00101002@Phycontrol2 DLL parameter settingstrr1, [r0, #DMC_PHYCONTROL0]ldrr1, =0x00101003@Dll onstrr1, [r0, #DMC_PHYCONTROL0]find_lock_val1:ldrr1, [r0, #DMC_PHYSTATUS]@Load Phystatus register valueand r2, r1, #0x7cmpr2, #0x7@Loop until DLL is lockedbnefind_lock_val1andr1, #0x3fc0 movr2, r1, LSL #18orrr2, r2, #0x100000orrr2, r2, #0x1000orrr1, r2, #0x3@Force Value lockingstrr1, [r0, #DMC_PHYCONTROL0]#if 1/* Memory margin test 10.01.05 */orrr1, r2, #0x1@DLL offstrr1, [r0, #DMC_PHYCONTROL0]#endifldrr0, =APB_DMC_1_BASEldrr1, =0x0FFF1010@auto refresh offstrr1, [r0, #DMC_CONCONTROL]ldr r1, =DMC1_MEMCONTROLstrr1, [r0, #DMC_MEMCONTROL]ldrr1, =DMC1_MEMCONFIG_0strr1, [r0, #DMC_MEMCONFIG0]ldrr1, =DMC1_MEMCONFIG_1strr1, [r0, #DMC_MEMCONFIG1]ldrr1, =0xff000000strr1, [r0, #DMC_PRECHCONFIG]ldrr1, =DMC1_TIMINGA_REFstrr1, [r0, #DMC_TIMINGAREF]ldrr1, =DMC1_TIMING_ROW@TimingRow@133MHzstrr1, [r0, #DMC_TIMINGROW]ldrr1, =DMC1_TIMING_DATAstrr1, [r0, #DMC_TIMINGDATA]ldrr1, =DMC1_TIMING_PWR@Timing Powerstrr1, [r0, #DMC_TIMINGPOWER]ldrr1, =0x07000000@chip0 Deselectstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x01000000@chip0 PALLstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x05000000@chip0 REFAstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x05000000@chip0 REFAstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00000032@chip0 MRSstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00020020@chip0 EMRSstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x07100000@chip1 Deselectstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x01100000@chip1 PALLstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x05100000@chip1 REFAstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x05100000@chip1 REFAstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00100032@chip1 MRSstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x00120020@chip0 EMRSstrr1, [r0, #DMC_DIRECTCMD]ldrr1, =0x0FFF10B0@ConControl auto refresh onstrr1, [r0, #DMC_CONCONTROL]ldrr1, =0xFFFF00FF@PwrdnConfigstrr1, [r0, #DMC_PWRDNCONFIG]ldrr1, =0x00212113@MemControlstrr1, [r0, #DMC_MEMCONTROL]#endif/* CONFIG_MCP_AC / CONFIG_MCP_H / CONFIG_MCP_B / CONFIG_MCP_D / CONFIG_MCP_N */movpc, lr