修改Tiny4412 uboot关闭MMU

材料： uboot_tiny4412-20130729.tgz dnw-linux.tar.gz

目的：使用dnw下载运行裸机程序。

原因：裸机开发中操作的都是物理地址，开启MMU之后，地址被映射，无法准确操作寄存器，所以需要关闭uboot中的mmu。

操作步骤：
1.修改uboot源码目录中：include/configs/tiny4412.h文件
修改第339行：
‘#define CONFIG_ENABLE_MMU’
为：
‘#undef CONFIG_ENABLE_MMU’
2.修改uboot源码目录中：board/samsung/tiny4412/config.mk文件
修改：
‘CONFIG_SYS_TEXT_BASE = 0xc3e00000’
为：
‘CONFIG_SYS_TEXT_BASE = 0x43e00000’
备注： Tiny4412开发板内存地址分布中0x40000000 – 0x8000000为内存地址，总共为1G。为什么这样分布及其它地址为什么东西，还有待查证！

修改重新编译后，打开System.map文件可以发现，里面的函数地址变为0x4开头的了，表示修改成功。

最后，我们使用烧写一个例子，验证printf函数能不能使用。
程序内容如下：

/* * 李柏章　Li Baizhang,  [e-mail], 2013-08,  */#include "regs.h"void (*printf)(char *, ...) = 0x43e11434;int test(void){    unsigned long value = 0;    __asm__ __volatile__ (        "mrs %0, cpsr\n"        : "=&r" (value)    );      printf(" value = 0x%x\n", value);    return 0;}

0x43e11434为System.map里面printf的前面的地址，读者最好确认一下，可能需要修改！

Makefile内容如下:

default:    arm-linux-gcc -c test.c  -o test.o    arm-linux-ld  -Ttext=0x70003000  test.o  -o test    arm-linux-objcopy  -O binary   test  test.binclean:    rm -f test.o  test  test.bin   *~ 

重要的是这个链接地址：0x70003000，dnw下载程序的时候，下载到地址就是0x70003000。链接地址的作用就是指明程序的储存地址，也就是让程序存放在0x70003000地方。（自己总结的！待深入了解。。）

编译完成后，就要使用dnw下载程序了，dnw驱动的安装，下载步骤不再详细说明，遇到问题，再多查查网络。
大概步骤如下：
1.开发板端进入uboot输入：dnw 70003000 开发板会等待连接。

2.此时主机会检测到usb设备，dnw Windows驱动win10一直装不上（尝试过很多资源，未成功！），所以只能使用Linux端的dnw。
安装驱动：insmod secbulk.ko
然后，dnw test.bin
连接成功并传输完成后，开发板会有反应，可能会出现校验和错误，但我发现程序还是可以成功运行，先不管。
3.传输完成后，输入go 70003000 跳转到这个地址去，就会执行程序，结果好像是打印cpu id吧！想要详细了解，需要查看arm处理器手册，里面有讲各个寄存器存储什么样的值，以及读取方式，指令等。

至此，实验完成。
reg.h

/* * 李柏章　Li Baizhang,  [e-mail], 2013-08,  */#pragma once#define gpiobase    0x11000000#define GPM4CON     (*(volatile unsigned long *)(gpiobase + 0x02E0)) #define GPM4DAT     (*(volatile unsigned long *)(gpiobase + 0x02E4))#define GPX3CON     (*(volatile unsigned long *)(gpiobase + 0x0C60))#define GPX4DAT     (*(volatile unsigned long *)(gpiobase + 0x0C64))#define EXT_INT43CON    (*(volatile unsigned long *)(gpiobase + 0x0e0c))#define EXT_INT43_MASK  (*(volatile unsigned long *)(gpiobase + 0x0f0c))#define EXT_INT43_PEND  (*(volatile unsigned long *)(gpiobase + 0x0f4c))#define gicbase     0x10480000#define ICCICR_CPU0 (*(volatile unsigned long *)(gicbase + 0x0))#define ICCPMR_CPU0 (*(volatile unsigned long *)(gicbase + 0x4))#define ICCBPR_CPU0 (*(volatile unsigned long *)(gicbase + 0x8))#define ICCIAR_CPU0     (*(volatile unsigned long *)(gicbase + 0xc))#define ICCEOIR_CPU0    (*(volatile unsigned long *)(gicbase + 0x10))#define ICCRPR_CPU0     (*(volatile unsigned long *)(gicbase + 0x14))#define ICCHPIR_CPU0    (*(volatile unsigned long *)(gicbase + 0x18))#define ICCABPR_CPU0    (*(volatile unsigned long *)(gicbase + 0x1c))#define INTEG_EN_C_CPU0 (*(volatile unsigned long *)(gicbase + 0x40))#define INTERRUPT_OUT_CPU0  (*(volatile unsigned long *)(gicbase + 0x44))#define ICCIIDR   (*(volatile unsigned long *)(gicbase + 0xfc))#define icdbase 0x10490000#define ICDDCR    (*(volatile unsigned long *)(icdbase + 0x0))#define ICDICTR   (*(volatile unsigned long *)(icdbase + 0x4))#define ICDIIDR   (*(volatile unsigned long *)(icdbase + 0x8))#define ICDISR0_CPU0 (*(volatile unsigned long *)(icdbase + 0x0080))#define ICDISR1_CPU0 (*(volatile unsigned long *)(icdbase + 0x0084))#define ICDISR2_CPU0 (*(volatile unsigned long *)(icdbase + 0x0088))#define ICDISR3_CPU0 (*(volatile unsigned long *)(icdbase + 0x008C))#define ICDISR4_CPU0 (*(volatile unsigned long *)(icdbase + 0x0090))#define ICDISER0_CPU0 (*(volatile unsigned long *)(icdbase + 0x0100))#define ICDISER1_CPU0 (*(volatile unsigned long *)(icdbase + 0x0104))#define ICDISER2_CPU0 (*(volatile unsigned long *)(icdbase + 0x0108))#define ICDISER3_CPU0 (*(volatile unsigned long *)(icdbase + 0x010C))#define ICDISER4_CPU0 (*(volatile unsigned long *)(icdbase + 0x0110))#define ICDICER0_CPU0 (*(volatile unsigned long *)(icdbase + 0x0180))#define ICDICER1_CPU0 (*(volatile unsigned long *)(icdbase + 0x0184))#define ICDICER2_CPU0 (*(volatile unsigned long *)(icdbase + 0x0188))#define ICDICER3_CPU0 (*(volatile unsigned long *)(icdbase + 0x018C))#define ICDICER4_CPU0 (*(volatile unsigned long *)(icdbase + 0x0190))#define ICDISPR0_CPU0 (*(volatile unsigned long *)(icdbase + 0x0200))#define ICDISPR1_CPU0 (*(volatile unsigned long *)(icdbase + 0x0204))#define ICDISPR2_CPU0 (*(volatile unsigned long *)(icdbase + 0x0208))#define ICDISPR3_CPU0 (*(volatile unsigned long *)(icdbase + 0x020C))#define ICDISPR4_CPU0 (*(volatile unsigned long *)(icdbase + 0x0210))#define ICDICPR0_CPU0 (*(volatile unsigned long *)(icdbase + 0x0280))#define ICDICPR1_CPU0 (*(volatile unsigned long *)(icdbase + 0x0284))#define ICDICPR2_CPU0 (*(volatile unsigned long *)(icdbase + 0x0288))#define ICDICPR3_CPU0 (*(volatile unsigned long *)(icdbase + 0x028C))#define ICDICPR4_CPU0 (*(volatile unsigned long *)(icdbase + 0x0290))#define ICDABR0_CPU0  (*(volatile unsigned long *)(icdbase + 0x0300))#define ICDABR1_CPU0  (*(volatile unsigned long *)(icdbase + 0x0304))#define ICDABR2_CPU0  (*(volatile unsigned long *)(icdbase + 0x0308))#define ICDABR3_CPU0  (*(volatile unsigned long *)(icdbase + 0x030C))#define ICDABR4_CPU0  (*(volatile unsigned long *)(icdbase + 0x0310))#define ICDIPR0_CPU0  (*(volatile unsigned long *)(icdbase + 0x0400)) #define ICDIPR1_CPU0  (*(volatile unsigned long *)(icdbase + 0x0404)) #define ICDIPR2_CPU0  (*(volatile unsigned long *)(icdbase + 0x0408)) #define ICDIPR3_CPU0  (*(volatile unsigned long *)(icdbase + 0x040C)) #define ICDIPR4_CPU0  (*(volatile unsigned long *)(icdbase + 0x0410)) #define ICDIPR5_CPU0  (*(volatile unsigned long *)(icdbase + 0x0414)) #define ICDIPR6_CPU0  (*(volatile unsigned long *)(icdbase + 0x0418)) #define ICDIPR7_CPU0  (*(volatile unsigned long *)(icdbase + 0x041C)) #define ICDIPR8_CPU0  (*(volatile unsigned long *)(icdbase + 0x0420)) #define ICDIPR9_CPU0  (*(volatile unsigned long *)(icdbase + 0x0424)) #define ICDIPR10_CPU0 (*(volatile unsigned long *)(icdbase + 0x0428))#define ICDIPR11_CPU0 (*(volatile unsigned long *)(icdbase + 0x042C))#define ICDIPR12_CPU0 (*(volatile unsigned long *)(icdbase + 0x0430))#define ICDIPR13_CPU0 (*(volatile unsigned long *)(icdbase + 0x0434))#define ICDIPR14_CPU0 (*(volatile unsigned long *)(icdbase + 0x0438))#define ICDIPR15_CPU0 (*(volatile unsigned long *)(icdbase + 0x043C))#define ICDIPR16_CPU0 (*(volatile unsigned long *)(icdbase + 0x0440))#define ICDIPR17_CPU0 (*(volatile unsigned long *)(icdbase + 0x0444))#define ICDIPR18_CPU0 (*(volatile unsigned long *)(icdbase + 0x0448))#define ICDIPR19_CPU0 (*(volatile unsigned long *)(icdbase + 0x044C))#define ICDIPR20_CPU0 (*(volatile unsigned long *)(icdbase + 0x0450))#define ICDIPR21_CPU0 (*(volatile unsigned long *)(icdbase + 0x0454))#define ICDIPR22_CPU0 (*(volatile unsigned long *)(icdbase + 0x0458))#define ICDIPR23_CPU0 (*(volatile unsigned long *)(icdbase + 0x045C))#define ICDIPR24_CPU0 (*(volatile unsigned long *)(icdbase + 0x0460))#define ICDIPR25_CPU0 (*(volatile unsigned long *)(icdbase + 0x0464))#define ICDIPR26_CPU0 (*(volatile unsigned long *)(icdbase + 0x0468))#define ICDIPR27_CPU0 (*(volatile unsigned long *)(icdbase + 0x046C))#define ICDIPR28_CPU0 (*(volatile unsigned long *)(icdbase + 0x0470))#define ICDIPR29_CPU0 (*(volatile unsigned long *)(icdbase + 0x0474))#define ICDIPR30_CPU0 (*(volatile unsigned long *)(icdbase + 0x0478))#define ICDIPR31_CPU0 (*(volatile unsigned long *)(icdbase + 0x047C))#define ICDIPR32_CPU0 (*(volatile unsigned long *)(icdbase + 0x0480))#define ICDIPR33_CPU0 (*(volatile unsigned long *)(icdbase + 0x0484))#define ICDIPR34_CPU0 (*(volatile unsigned long *)(icdbase + 0x0488))#define ICDIPR35_CPU0 (*(volatile unsigned long *)(icdbase + 0x048C))#define ICDIPR36_CPU0 (*(volatile unsigned long *)(icdbase + 0x0490))#define ICDIPR37_CPU0 (*(volatile unsigned long *)(icdbase + 0x0494))#define ICDIPR38_CPU0 (*(volatile unsigned long *)(icdbase + 0x0498))#define ICDIPR39_CPU0 (*(volatile unsigned long *)(icdbase + 0x049C))#define ICDIPTR0_CPU0  (*(volatile unsigned long *)(icdbase + 0x0800))#define ICDIPTR1_CPU0  (*(volatile unsigned long *)(icdbase + 0x0804))#define ICDIPTR2_CPU0  (*(volatile unsigned long *)(icdbase + 0x0808))#define ICDIPTR3_CPU0  (*(volatile unsigned long *)(icdbase + 0x080C))#define ICDIPTR4_CPU0  (*(volatile unsigned long *)(icdbase + 0x0810))#define ICDIPTR5_CPU0  (*(volatile unsigned long *)(icdbase + 0x0814))#define ICDIPTR6_CPU0  (*(volatile unsigned long *)(icdbase + 0x0818))#define ICDIPTR7_CPU0  (*(volatile unsigned long *)(icdbase + 0x081C))#define ICDIPTR8_CPU0  (*(volatile unsigned long *)(icdbase + 0x0820))#define ICDIPTR9_CPU0  (*(volatile unsigned long *)(icdbase + 0x0824))#define ICDIPTR10_CPU0 (*(volatile unsigned long *)(icdbase + 0x0828))#define ICDIPTR11_CPU0 (*(volatile unsigned long *)(icdbase + 0x082C))#define ICDIPTR12_CPU0 (*(volatile unsigned long *)(icdbase + 0x0830))#define ICDIPTR13_CPU0 (*(volatile unsigned long *)(icdbase + 0x0834))#define ICDIPTR14_CPU0 (*(volatile unsigned long *)(icdbase + 0x0838))#define ICDIPTR15_CPU0 (*(volatile unsigned long *)(icdbase + 0x083C))#define ICDIPTR16_CPU0 (*(volatile unsigned long *)(icdbase + 0x0840))#define ICDIPTR17_CPU0 (*(volatile unsigned long *)(icdbase + 0x0844))#define ICDIPTR18_CPU0 (*(volatile unsigned long *)(icdbase + 0x0848))#define ICDIPTR19_CPU0 (*(volatile unsigned long *)(icdbase + 0x084C))#define ICDIPTR20_CPU0 (*(volatile unsigned long *)(icdbase + 0x0850))#define ICDIPTR21_CPU0 (*(volatile unsigned long *)(icdbase + 0x0854))#define ICDIPTR22_CPU0 (*(volatile unsigned long *)(icdbase + 0x0858))#define ICDIPTR23_CPU0 (*(volatile unsigned long *)(icdbase + 0x085C))#define ICDIPTR24_CPU0 (*(volatile unsigned long *)(icdbase + 0x0860))#define ICDIPTR25_CPU0 (*(volatile unsigned long *)(icdbase + 0x0864))#define ICDIPTR26_CPU0 (*(volatile unsigned long *)(icdbase + 0x0868))#define ICDIPTR27_CPU0 (*(volatile unsigned long *)(icdbase + 0x086C))#define ICDIPTR28_CPU0 (*(volatile unsigned long *)(icdbase + 0x0870))#define ICDIPTR29_CPU0 (*(volatile unsigned long *)(icdbase + 0x0874))#define ICDIPTR30_CPU0 (*(volatile unsigned long *)(icdbase + 0x0878))#define ICDIPTR31_CPU0 (*(volatile unsigned long *)(icdbase + 0x087C))#define ICDIPTR32_CPU0 (*(volatile unsigned long *)(icdbase + 0x0880))#define ICDIPTR33_CPU0 (*(volatile unsigned long *)(icdbase + 0x0884))#define ICDIPTR34_CPU0 (*(volatile unsigned long *)(icdbase + 0x0888))#define ICDIPTR35_CPU0 (*(volatile unsigned long *)(icdbase + 0x088C))#define ICDIPTR36_CPU0 (*(volatile unsigned long *)(icdbase + 0x0890))#define ICDIPTR37_CPU0 (*(volatile unsigned long *)(icdbase + 0x0894))#define ICDIPTR38_CPU0 (*(volatile unsigned long *)(icdbase + 0x0898))#define ICDIPTR39_CPU0 (*(volatile unsigned long *)(icdbase + 0x089C))#define ICDICFR0_CPU0 (*(volatile unsigned long *)(icdbase + 0x0C00))#define ICDICFR1_CPU0 (*(volatile unsigned long *)(icdbase + 0x0C04))#define ICDICFR2_CPU0 (*(volatile unsigned long *)(icdbase + 0x0C08))#define ICDICFR3_CPU0 (*(volatile unsigned long *)(icdbase + 0x0C0C))#define ICDICFR4_CPU0 (*(volatile unsigned long *)(icdbase + 0x0C10))#define ICDICFR5_CPU0 (*(volatile unsigned long *)(icdbase + 0x0C14))#define ICDICFR6_CPU0 (*(volatile unsigned long *)(icdbase + 0x0C18))#define ICDICFR7_CPU0 (*(volatile unsigned long *)(icdbase + 0x0C1C))#define ICDICFR8_CPU0 (*(volatile unsigned long *)(icdbase + 0x0C20))#define ICDICFR9_CPU0 (*(volatile unsigned long *)(icdbase + 0x0C24))#define PPI_STATUS_CPU0 (*(volatile unsigned long *)(icdbase + 0x0D00))#define SPI_STATUS0 (*(volatile unsigned long *)(icdbase + 0x0D04))#define SPI_STATUS1 (*(volatile unsigned long *)(icdbase + 0x0D08))#define SPI_STATUS2 (*(volatile unsigned long *)(icdbase + 0x0D0C))#define SPI_STATUS3 (*(volatile unsigned long *)(icdbase + 0x0D10))#define ICDSGIR  (*(volatile unsigned long *)(icdbase + 0x0f00))#define wdtbase 0x10060000#define WTCON    (*(volatile unsigned long *)(wdtbase + 0x0000)) #define WTDAT    (*(volatile unsigned long *)(wdtbase + 0x0004)) #define WTCNT    (*(volatile unsigned long *)(wdtbase + 0x0008)) #define WTCLRINT (*(volatile unsigned long *)(wdtbase + 0x000C)) #define pwmbase 0x139D0000#define TCFG0       (*(volatile unsigned long *)(pwmbase + 0x0000)) #define TCFG1       (*(volatile unsigned long *)(pwmbase + 0x0004)) #define TCON        (*(volatile unsigned long *)(pwmbase + 0x0008)) #define TCNTB0      (*(volatile unsigned long *)(pwmbase + 0x000C)) #define TCMPB0      (*(volatile unsigned long *)(pwmbase + 0x0010)) #define TCNTO0      (*(volatile unsigned long *)(pwmbase + 0x0014)) #define TCNTB1      (*(volatile unsigned long *)(pwmbase + 0x0018)) #define TCMPB1      (*(volatile unsigned long *)(pwmbase + 0x001C)) #define TCNTO1      (*(volatile unsigned long *)(pwmbase + 0x0020)) #define TCNTB2      (*(volatile unsigned long *)(pwmbase + 0x0024)) #define TCMPB2      (*(volatile unsigned long *)(pwmbase + 0x0028)) #define TCNTO2      (*(volatile unsigned long *)(pwmbase + 0x002C)) #define TCNTB3      (*(volatile unsigned long *)(pwmbase + 0x0030)) #define TCMPB3      (*(volatile unsigned long *)(pwmbase + 0x0034)) #define TCNTO3      (*(volatile unsigned long *)(pwmbase + 0x0038)) #define TCNTB4      (*(volatile unsigned long *)(pwmbase + 0x003C)) #define TCNTO4      (*(volatile unsigned long *)(pwmbase + 0x0040)) #define TINT_CSTAT  (*(volatile unsigned long *)(pwmbase + 0x0044)) 

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