算法机ASM和算法流程图ASMc

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ASMc的例子是一个用流水线的方式将8比特字节流连续的装配成16比特字的抽取器（decimator）模块的ASMD编码。

图算法机例子，2：1总线抽取器decimator：

图使用ASMD建模如下，由控制器和数据通道组成的ASMD：

图总线抽取器的算法流程图ASMc：

总线抽取器的Verilog HDL代码：

module decimator(clk,rst_n,data,q);   input clk, rst_n;input [7:0] data;output reg [15:0] q;   reg load_p, load_q ;reg [7:0] p1, p0;reg [1:0] state;localparam s0=2'b00;localparam s1=2'b01;localparam s2=2'b10;always @ (posedge clk )     begin :F1            if(!rst_n)                  p1<=0;else if(load_p)                 p1<=data;                end                      always @ (posedge clk )     begin : F0            if(!rst_n)               p0<=0;                else if(load_p)                 p0<=p1;                end                      always @ (posedge clk )     begin : Q            if(!rst_n)                 q<=0;                else if(load_q)                q<={p1,p0};                 end                      always @(posedge clk)     begin : ASM          if(!rst_n)        begin  load_p <= 0 ;  load_q <= 0 ;  state <= s0 ;  end else       case (state)                       s0: begin              load_p <= 1; state <= s1 ;                         end   s1:begin       load_p<=1; load_q<=0; state <= s2 ;             end         s2:begin    load_p <=1;    load_q <= 1; state <=s1;    end endcase     end          endmodule

总线抽取器的Testbench:

`timescale 1ns/1psmodule decimator_tb;    reg clk, rst_n; reg [7:0] data; wire [15:0] q;                                decimator dut(.clk(clk),.rst_n(rst_n),.data(data),.q(q));                              initial begin           clk =1 ;           rst_n=0; data = 0;  #200 @ (posedge clk) rst_n =1 ; #200 forever begin     @ (posedge clk) data = 8'h10;     @ (posedge clk) data = 8'h32;      @ (posedge clk) data = 8'h54;   @ (posedge clk) data = 8'h76;  @ (posedge clk) data = 8'h98;  @ (posedge clk) data = 8'hba;    @ (posedge clk) data = 8'hdc;  @ (posedge clk) data = 8'hfe; end       end  always #10 clk =~clk ; initial #2000 $stop;  endmodule

总线抽取器的Modelsim仿真：

输出数据设置为16进制。

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