阶段二设计

2-1：多周期-恒最大值计数-显示电路

module cnt_synt(CLK, CNT, OV);input CLK ;output reg[31:0] CNT;output reg OV ;parameter MAX_VAL = 50_000_000;always @ (posedge CLK) beginif(CNT < MAX_VAL)    CNT <= CNT+ 1'b1 ;else    CNT <= 0;endalways @ (CNT) begin if (CNT==MAX_VAL) OV = 1'b1; else OV = 1'b0;endendmodulemodule cnt_0to9(CLK, EN, IN,OUT);input CLK, EN ;output reg [7:0] OUT;output reg [3:0] IN ;always @ (posedge CLK ) begin  if(EN) begin    if(IN < 9)    IN <= IN + 1'b1 ;    else    IN <= 0;  end   else  IN <= IN ;endalways @ (IN) begin    case(IN)    4'h0: OUT = 8'b1100_0000;    4'h1: OUT = 8'b1111_1001;    4'h2: OUT = 8'b1010_0100;    4'h3: OUT = 8'b1011_0000;    4'h4: OUT = 8'b1001_1001;    4'h5: OUT = 8'b1001_0010;    4'h6: OUT = 8'b1000_0010;    4'h7: OUT = 8'b1111_1000;    4'h8: OUT = 8'b1000_0000;    4'h9: OUT = 8'b1001_0000;    endcaseendendmodule![singletap波形图](http://img.blog.csdn.net/20170706114602121?watermark/2/text/aHR0cDovL2Jsb2cuY3Nkbi5uZXQvSFlMXzIwMTU=/font/5a6L5L2T/fontsize/400/fill/I0JBQkFCMA==/dissolve/70/gravity/SouthEast)``

2-2：LED的亮度调节

module cnt_synt(CLK, CNT,OV);input CLK ;output reg[31:0]CNT;output reg OV;parameter MAX_VAL=500_000;always @ (posedge CLK) begin  if(CNT < MAX_VAL)  CNT <= 1'b1+CNT ;  else  CNT <= 0;endalways @ (CNT) beginif (CNT == MAX_VAL )OV = 1'b1;elseOV = 1'b0;endendmodulemodule duty_division(CLK, EN, OUT);input CLK ,EN;output reg [3:0] OUT ;reg [7:0]COUNT;always @ (posedge CLK) beginif(EN)begin    if(COUNT<99)    COUNT <= COUNT + 1'b1;    else    COUNT <= 0;    if((COUNT >= 0)&&(COUNT <50))    OUT[0] <= 1;    else    OUT[0] <=0;    if((COUNT >= 0)&&(COUNT <25))    OUT[1] <= 1;    else    OUT[1] <=0;    if((COUNT >= 0)&&(COUNT <100/8))    OUT[2] <= 1;    else    OUT[2] <=0;    if((COUNT >= 0)&&(COUNT <100/16))    OUT[3] <= 1;    else    OUT[3] <=0;    endelse    COUNT<= COUNT;endendmodule

2-3:0到9循环计数，0最暗，9最亮

module cnt_synt(CLK , CNT ,OV);input CLK ;output reg [31:0] CNT;output reg OV ;parameter MAX_VAL = 50000_000;always @ (posedge CLK ) beginif(CNT < MAX_VAL)    CNT <= CNT+ 1'b1;    else    CNT <= 0;endalways @(CNT) beginif(CNT== MAX_VAL)    OV = 1'b1;    else    OV = 1'b0;endendmodulemodule cnt_en_0to9(CLK, EN ,CNT);input CLK ,EN;output reg [3:0]CNT ;always @ (posedge CLK) beginif(EN)begin    if(CNT <9)    CNT <= CNT+ 1'b1 ;    else    CNT <= 0 ;    endelse    CNT <= CNT;endendmodulemodule duty_division(CLK,IN,PULSE);input CLK ;input [3:0]IN;output reg PULSE ;reg [6:0] COUNT;always @ (posedge CLK)begin    if(COUNT < 10 )    COUNT <= COUNT + 1'b1;    else    COUNT <= 0;    if((COUNT >= 0 )&& (COUNT <= IN))    PULSE <= 1;    else    PULSE <= 0;endendmodulemodule dec_4to7(IN,EN,OUT);input EN ;input [3:0]IN;output reg[7:0] OUT;always @(IN) begin  if(EN) begincase(IN)4'h1: OUT = 8'b1111_1001;4'h2: OUT = 8'b1010_0100;4'h3: OUT = 8'b1011_0000;4'h4: OUT = 8'b1001_1001;4'h5: OUT = 8'b1001_0010;4'h6: OUT = 8'b1000_0010;4'h7: OUT = 8'b1111_1000;4'h8: OUT = 8'b1000_0000;4'h9: OUT = 8'b1001_0000;4'h0: OUT = 8'b1100_0000;default: OUT = 8'b1111_1111;endcaseendelseOUT = 8'b1111_1111;endendmodule