The condition code flags

1. Condition code meaning

The N, Z, C, and V (Negative, Zero, Carry and oVerflow) bits are collectively known as the condition code flags, often referred to as flags. The condition code flags in the CPSR can be tested by most instructions to determine whether the instruction is to be executed.
The new condition code flags (after the instruction has been executed) usually mean:

1.1 Negative

N Is set to bit 31 of the result of the instruction. If this result is regarded as a two’s complement signed integer, then N = 1 if the result is negative and N = 0 if it is positive or zero.

1.2 Zero

Z Is set to 1 if the result of the instruction is zero (this often indicates an equal result from a comparison), and to 0 otherwise.

1.3 Carry

C Is set in one of four ways:
• For an addition, including the comparison instruction CMN, C is set to 1 if the addition produced a carry (that is, an unsigned overflow), and to 0 otherwise.
• For a subtraction, including the comparison instruction CMP, C is set to 0 if the subtraction produced a borrow (that is, an unsigned underflow), and to 1 otherwise.
• For non-addition/subtractions that incorporate a shift operation, C is set to the last bit shifted out of the value by the shifter.
• For other non-addition/subtractions, C is normally left unchanged (but see the individual instruction descriptions for any special cases).

1.4 oVerflow

V Is set in one of two ways:
• For an addition or subtraction, V is set to 1 if signed overflow occurred, regarding the operands and result as two’s complement signed integers.
• For non-addition/subtractions, V is normally left unchanged (but see the individual instruction descriptions for any special cases).

2. The condition field

Most ARM instructions can be conditionally executed, which means that they only have their normal effect on the programmers’ model state, memory and coprocessors if the N, Z, C and V flags in the CPSR satisfy a condition specified in the instruction. If the flags do not satisfy this condition, the instruction acts as a NOP: that is, execution advances to the next instruction as normal, including any relevant checks for interrupts and Prefetch Aborts, but has no other effect.
Most instruction mnemonics can be extended with the letters defined in the mnemonic extension field.If the always (AL) condition is specified, the instruction is executed irrespective of the value of the condition code flags. The absence of a condition code on an instruction mnemonic implies the AL condition code.