单脉冲发生器设计

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一、架构设计

二、依据时序图的FSM 控制信号设计(摩尔机类型)

三、状态转移图（STG：Moore，NBD）

摩尔机TP 图：

四、依据时序图的FSM 控制信号设计(Mealy 机类型)

五、状态转移图（STG：Mealy，EBD）

米利机TP 图：

顶层代码：

module wd_mod(clk, rst_n, wd, en, p_out);input clk;input rst_n;input [7:0]wd;output reg en;output reg p_out;parameter lw = 4;reg count_en;reg [7:0]count;reg [3:0]state;localparam s0 = 4'b0000;localparam s1 = 4'b0001;localparam s2 = 4'b0010;localparam s3 = 4'b0011;localparam s4 = 4'b0100;localparam s5 = 4'b0101;localparam s6 = 4'b0110;localparam s7 = 4'b0111;localparam s8 = 4'b1000;localparam s9 = 4'b1001;localparam s10 = 4'b1010;localparam s11 = 4'b1011;localparam s12 = 4'b1100;localparam s13 = 4'b1101;localparam s14 = 4'b1110;localparam s15 = 4'b1111;always @ (posedge clk)beginif(!rst_n || !count_en)begincount <= 0;endelsebegincount <= count + 1;endendalways @ (posedge clk)beginif (!rst_n)beginp_out <= 0;count_en <= 0;state <= s0;en <= 0;endelsebegincase(state)s0:beginen <= 1;state <= s1;ends1:beginstate <= s2;ends2:beginp_out <= 1;count_en <= 1;state <= s3;ends3:beginif(count < wd - 3)beginstate <= s3;endelsebeginstate <= s4;endends4:begincount_en <= 0;state <= s5;ends5:beginp_out <= 0;count_en <= 1;en <= 0;state <= s6;ends6:beginif(count < lw - 3)beginstate <= s6;endelsebeginstate <= s7;endends7:begincount_en <= 0;en <= 1;state <= s8;ends8:beginp_out <= 1;count_en <= 1;state <= s3;endendcaseendendendmodule

module wd_gen(clk, rst_n, en, wd);input clk;input rst_n;input en;output reg [7:0] wd;reg state;localparam s0 = 1'b0;localparam s1 = 1'b1;always @ (posedge clk)beginif (!rst_n)beginwd <= 0;state <= s0;endelsecase (state)s0:if (!en)state <= s0;elsebeginwd <= 4+({$random} % 16);state <= s1;ends1:if (en)state <= s1;elsebeginstate <= s0;wd <= 0;endendcaseendendmodule

modelsim:

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