基于官方库的STM32操作U盘注意的问题

前几天调试了stm32f105基于官方库STM32_USB-Host-Device_Lib_V2.2.0的示例代码读取优盘，调试成功。
在官方库文件STM32_USB-Host-Device_Lib_V2.2.0下Project/USB_Host_Examples/MSC，打开工程。根据你的外部晶振，需要修改系统频率和USB时钟设置。
我用的外部晶振是8M的为例，打开文件system_stm32f10x.c文件，找到函数static void SetSysClockTo72(void)
以下为源码

/**  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2   *          and PCLK1 prescalers.   * @note   This function should be used only after reset.  * @param  None  * @retval None  */static void SetSysClockTo72(void){    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;    /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/        /* Enable HSE */        RCC->CR |= ((uint32_t)RCC_CR_HSEON);    /* Wait till HSE is ready and if Time out is reached exit */    do    {        HSEStatus = RCC->CR & RCC_CR_HSERDY;        StartUpCounter++;      } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));    if ((RCC->CR & RCC_CR_HSERDY) != RESET)    {        HSEStatus = (uint32_t)0x01;    }    else    {        HSEStatus = (uint32_t)0x00;    }      if (HSEStatus == (uint32_t)0x01)    {        /* Enable Prefetch Buffer */        FLASH->ACR |= FLASH_ACR_PRFTBE;        /* Flash 2 wait state */        FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);        FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;            /* HCLK = SYSCLK */        RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;        /* PCLK2 = HCLK */        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;        /* PCLK1 = HCLK */        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;        /* Configure PLLs ------------------------------------------------------*/        /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */        /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */        RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |                                  RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);        RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |                                 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);        /* Enable PLL2 */        RCC->CR |= RCC_CR_PLL2ON;        /* Wait till PLL2 is ready */        while((RCC->CR & RCC_CR_PLL2RDY) == 0)        {        }        /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */         RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);        RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |                                 RCC_CFGR_PLLMULL9);         /* Enable PLL */        RCC->CR |= RCC_CR_PLLON;        /* Wait till PLL is ready */        while((RCC->CR & RCC_CR_PLLRDY) == 0)        {        }        /* Select PLL as system clock source */        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));        RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;            /* Wait till PLL is used as system clock source */        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)        {        }    }    else    { /* If HSE fails to start-up, the application will have wrong clock          configuration. User can add here some code to deal with this error */    }}

修改为下面代码

/**  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2   *          and PCLK1 prescalers.   * @note   This function should be used only after reset.  * @param  None  * @retval None  */static void SetSysClockTo72(void){    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;    /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/        /* Enable HSE */        RCC->CR |= ((uint32_t)RCC_CR_HSEON);    /* Wait till HSE is ready and if Time out is reached exit */    do    {        HSEStatus = RCC->CR & RCC_CR_HSERDY;        StartUpCounter++;      } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));    if ((RCC->CR & RCC_CR_HSERDY) != RESET)    {        HSEStatus = (uint32_t)0x01;    }    else    {        HSEStatus = (uint32_t)0x00;    }      if (HSEStatus == (uint32_t)0x01)    {        /* Enable Prefetch Buffer */        FLASH->ACR |= FLASH_ACR_PRFTBE;        /* Flash 2 wait state */        FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);        FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;            /* HCLK = SYSCLK */        RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;        /* PCLK2 = HCLK */        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;        /* PCLK1 = HCLK */        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;        /* Configure PLLs ------------------------------------------------------*/        //40=8/2*10 修改后        /* PLL2 configuration: PLL2CLK = (HSE / 2) * 10 = 40 MHz */        /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */        RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |                                  RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);        //RCC_CFGR2_PREDIV2_DIV2 | RCC_CFGR2_PLL2MUL10修改后        RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV2 | RCC_CFGR2_PLL2MUL10 |                                 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);        /* Enable PLL2 */        RCC->CR |= RCC_CR_PLL2ON;        /* Wait till PLL2 is ready */        while((RCC->CR & RCC_CR_PLL2RDY) == 0)        {        }        /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */         RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);        RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |                                 RCC_CFGR_PLLMULL9);         /* Enable PLL */        RCC->CR |= RCC_CR_PLLON;        /* Wait till PLL is ready */        while((RCC->CR & RCC_CR_PLLRDY) == 0)        {        }        /* Select PLL as system clock source */        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));        RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;            /* Wait till PLL is used as system clock source */        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)        {        }    }    else    { /* If HSE fails to start-up, the application will have wrong clock          configuration. User can add here some code to deal with this error */    }}