Arm history introduction

 

The ARM processor architecture provides support for the 32-bit ARM and 16-bit Thumb^®Instruction Set Architectures (ISAs) along with architecture extensionsto provide support for Java acceleration (Jazelle™), security (TrustZone™), Intelligent Energy Manager (IEM), SIMD, and NEON^TM technologies.

TheARM ISA is constantly improving to meet the increasing demands ofleading edge applications developers, while retaining the backwardscompatibility necessary to protect investment in software development.

ARMv4
Theoldest version of the processor architecture supported today. Allprevious versions are now obsolete. Implementations include somemembers of the ARM7™ processor family and Intel StrongARM^® processors. ARMv4 can be considered a 32-bit ISA operating in a 32-bit address space.

ARMv4T
The ARMv4T processor architecture added the 16-bit Thumb® instructionset which enabled compilers to generate more compact code (memorysavings of up to 35% over the equivalent 32-bit code), while retainingall the benefits of a 32-bit system.

ARMv5TE
In 1999, the ARMv5TE processor architecture introduced improvements to the Thumb architecture, along with ARM ‘Enhanced’ DSP (digital signal processing) instruction set extensions to the ARM ISA.

TheThumb changes added a few new instructions along with improvements toThumb/ARM interworking, greatly improving compiler capabilities and theability to mix and match ARM versus Thumb routines to balance code sizeand performance.

The enhanced DSP instructions include supportfor saturated arithmetic, and provide up to 70% performance improvementfor audio DSP applications. Many systems require the flexibility of amicrocontroller combined with the data-processing capability of a DSP,historically forcing designers to compromise performance with cost, oradopt complex multi processor strategies. The ‘E’ instruction setextensions were designed to provide a DSP capability in a generalpurpose CPU, resulting in improved performance and flexibility.

ARMv5TEJ
In2000, the ARMv5TEJ processor architecture added the Jazelle® technologyextension to support Java acceleration technology, which isparticularly suited to small memory footprint designs. Jazelletechnology’s acceleration of Java bytecodes provides significantlyhigher performance than a software-only based Java Virtual Machine(JVM), accelerating Java execution by 8x and providing an 80% reductionin power consumption compared to a non Java-accelerated core. Thisfunctionality gives platform developers increased freedom to run Javacode alongside established operating systems (OS) and applications onan ARM processor.

ARMv6
TheARMv6 processor architecture, announced in 2001, features improvementsin many areas covering the memory system, improved exception handlingand better support for multiprocessing environments. ARMv6 alsoincludes media instructions to support Single Instruction Multiple Data (SIMD)software execution. The SIMD extensions are optimized for a broad rangeof software applications including video and audio codecs, where theextensions increase performance by up to four times. In additionThumb-2 and TrustZone® technologies were introduced as variants of theARMv6 architecture. The first implementation of the ARMv6 architecture was the ARM1136J(F)-S^TM processor announced in Spring 2002, followed by the ARM1156T2(F)-S^TM and the ARM1176JZ(F)-S^TM processors in 2003.

ARMv7
The ARMv7 processor architecture lies below the Cortex^TM family of processors and defines three distinct processor profiles: the A profile for sophisticated, virtual memory-based OSand user applications; the R profile for real-time systems; and the Mprofile optimized for microcontroller and low-cost applications.

All ARMv7 architecture profiles implement Thumb® -2 technologywhich is built on the foundation of the ARM industry-leading Thumb codecompression technology, while retaining complete code compatibilitywith existing ARM solutions. The ARMv7 architecture also includes the NEON™ technologyextensions to increase DSP and media processing throughput by up to 400percent, and offers improved floating point support to address theneeds of next generation 3D graphics and games physics, as well astraditional embedded control applications.

NEON Media Acceleration Technology
ARM NEON technologyis an architecture option with the ARMv7A architecture and is designedto address the demands of next generation high-performance, mediaintense, low power mobile handheld devices. NEON technology is a64/128-bit hybrid SIMD architecture, developed by ARM to accelerate theperformance of multimedia and signal processing applications includingvideo encode/decode, 3D graphics, speech processing, compressed audiodecoding, image processing, telephony and sound synthesis.

Vector Floating Point (VFP)
VectorFloating Point (VFP) coprocessor support is an architecture option. TheVFP architecture supports single and double precision floating pointarithmetic, and is fully IEEE 754 compliant with suitable softwarelibrary support. The VFP architecture also includes a fullydeterministic ‘Run fast Mode’.

Provision of ahardware floating point is essential for many applications, and can beused as part of a System on Chip (SoC) design flow using technicalcomputing tools (eg MatLab® and MATRIXx®) to directly model the systemand derive the application code. The vector processing capability ofthe ARM VFP can be used to increase performance of imaging applicationssuch as scaling, 2D and 3D transforms, font generation, and digitalfilters.

ARM currently has VFP support for the ARM9™, ARM10™ and ARM11™ processor families: VFP9-S™ and VFP10™. Additional VFP options, VFPv3, were introduced with the ARMv7 architecture.

ARM TrustZone
The ARM TrustZone extensionsprovide hardware support for two separate address spaces, such thatcode executing in the non-secure world cannot gain access to anyaddress space marked as secure. A new monitor mode supports transitionbetween the two worlds.
 
The technology provides a secureenvironment for system features such as key management and/orauthentication mechanisms enabled by an open OS. The protectionprovided by the technology is necessary for consumer privacy andextending a range of services, such as mobile banking and multimediaentertainment, to widespread consumer adoption and use.

Thumb-2 Technology
ARM and Thumb code each execute in their own processor state. Thumb-2 coretechnology adds a mixed mode capability, defining a new set of 32-bitinstructions that execute alongside traditional 16-bit instructions inThumb state. This reduces, or can remove, the need for balancing ARMand Thumb code in a system, providing ‘ARM levels of performance’ with‘Thumb code density’.

Thumb-2 technologybuilds on the success of Thumb technology, adding to ARM’s strengths asthe leading supplier of low power, high performance processors andsystems, supply cost effective and timely solutions across a wide rangeof market segments.

Other Related Technologies
Inaddition to the above technologies, several other system technologieswith their own architecture provisions are available from ARM.

Debug and Trace 
ARM'sdebug and trace tools enable system developers to quickly debugreal-time software, and to trace instruction execution and associatedprogram data at full core speed. The debug and trace offering includeshost based tools along with components such as EmbeddedICE, Embedded Trace Macrocell (ETM™), and the latest CoreSight™ technology, which form part of a modern SoC.

AMBA®
TheAMBA® protocol is an open standard, on-chip bus specification thatdetails a strategy for the interconnection and management of functionalblocks that makes up a System-on-Chip (SoC). It facilitates"right-first-time" development of embedded processors with one or moreCPU/signal processors and multiple peripherals. The AMBA protocolenhances a reusable design methodology by defining a common backbonefor SoC modules. 

ARM Intelligent Energy Manager
ARM Intelligent Energy Manager (IEM^TM)technology implements advanced algorithms to optimally balanceprocessor workload and energy consumption, while maximizing systemresponsiveness to meet end-user performance expectations. TheIntelligent Energy Manager technology works with the OS andapplications running on the mobile phone to dynamically adjust therequired CPU performance level through a standard programmer's model.