Place:1136-This design contains a global buffer instance
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在使用chipscope进行FPGA工程仿真时，出现上图报错。原因是在cdc文件中加入了一个信号CLK_BEI,而选择的trigger信号为clk1(是由CLK_BEI分频而来)，所以报错。
解决办法，去掉CLK_BEI信号即可。
产生类似问题时要检查报错信号和触发信号的关系，多是关系紧密的，比如在本例中CLK_BEI经过50分频产生了clk1，但是在cdc中使用clk1来触发观察CLK_BEI显然是错误的，逻辑上已经错了。
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