串口发送32bit数据Verilog

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发送机部分如下：
`define NUMBER 41//32bit字符数据的长度（要加上起始位和停止位）//`define NUMBER 11//8bit字符数据//`define NUMBER 21//16bit字符数据//`define NUMBER 31//24bit字符数据`define NUMWIDTH 5//NUMBER的范围0~64//`define NUMWIDTH 4//NUMBER的范围0~32//`define NUMWIDTH 3//NUMBER的范围0~16module my_uart_tx(clk,rst_n,rx_data,rx_int,rs232_tx,clk_bps,bps_start);input clk;// 40MHzinput rst_n;//input clk_bps;// clk_bps_rinput rx_int;//output rs232_tx;// RS232output bps_start;//input[`WIDTH-1:0] rx_data;//将接收的数据发送到PC上reg[`WIDTH-1:0] tx_data;//reg[`NUMWIDTH:0] num;//需要改宽度//---------------------------------------------------------reg rx_int0,rx_int1,rx_int2;//rx_intwire neg_rx_int;// rx_intalways @ (posedge clk or negedge rst_n) beginif(!rst_n) beginrx_int0 <= 1'b0;rx_int1 <= 1'b0;rx_int2 <= 1'b0;endelse beginrx_int0 <= rx_int;rx_int1 <= rx_int0;rx_int2 <= rx_int1;endendassign neg_rx_int =  ~rx_int1 & rx_int2;////---------------------------------------------------------reg bps_start_r;reg tx_en;//always @ (posedge clk or negedge rst_n) beginif(!rst_n) beginbps_start_r <= 1'bz;tx_en <= 1'b0;tx_data <= 8'd0;endelse if(neg_rx_int) begin//bps_start_r <= 1'b1;tx_data <= rx_data;tx_en <= 1'b1;//endelse if( num==`NUMBER) beginbps_start_r <= 1'b0;tx_en <= 1'b0;endendassign bps_start = bps_start_r;//---------------------------------------------------------reg rs232_tx_r;always @ (posedge clk or negedge rst_n) beginif(!rst_n) beginnum <= 0;rs232_tx_r <= 1'b1;endelse if(tx_en)beginif(clk_bps)beginnum <= num+1'b1;case (num)0: rs232_tx_r <= 1'b0; //起始位1: rs232_tx_r <= tx_data[0];//数据位[7:0]2: rs232_tx_r <= tx_data[1];3: rs232_tx_r <= tx_data[2];4: rs232_tx_r <= tx_data[3];5: rs232_tx_r <= tx_data[4];6: rs232_tx_r <= tx_data[5];7: rs232_tx_r <= tx_data[6];8: rs232_tx_r <= tx_data[7];9: rs232_tx_r <= 1'b1;//停止位10: rs232_tx_r <= 1'b0; //起始位11: rs232_tx_r <= tx_data[8];//数据位[15:8]12: rs232_tx_r <= tx_data[9];13: rs232_tx_r <= tx_data[10];14: rs232_tx_r <= tx_data[11];15: rs232_tx_r <= tx_data[12];16: rs232_tx_r <= tx_data[13];17: rs232_tx_r <= tx_data[14];18: rs232_tx_r <= tx_data[15];19: rs232_tx_r <= 1'b1;//停止位20: rs232_tx_r <= 1'b0; //起始位21: rs232_tx_r <= tx_data[16];//数据位[23:9]22: rs232_tx_r <= tx_data[17];23: rs232_tx_r <= tx_data[18];24: rs232_tx_r <= tx_data[19];25: rs232_tx_r <= tx_data[20];26: rs232_tx_r <= tx_data[21];27: rs232_tx_r <= tx_data[22];28: rs232_tx_r <= tx_data[23];29: rs232_tx_r <= 1'b1;//停止位30: rs232_tx_r <= 1'b0; //起始位31: rs232_tx_r <= tx_data[24];//数据位[31:24]32: rs232_tx_r <= tx_data[25];33: rs232_tx_r <= tx_data[26];34: rs232_tx_r <= tx_data[27];35: rs232_tx_r <= tx_data[28];36: rs232_tx_r <= tx_data[29];37: rs232_tx_r <= tx_data[30];38: rs232_tx_r <= tx_data[31];39: rs232_tx_r <= 1'b1;//停止位 default: rs232_tx_r <= 1'b1;endcaseendelse if(num==`NUMBER) num <=0;endendassign rs232_tx = rs232_tx_r;endmodule
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