Optimized Signal Integrity

 

 

1. Introduction

 

It is surprising how many electrical engineers will design modern high-speed digital circuit boards without handling the transmission line issues. The same engineers would not release an analog design board to production without first scoping out the intermediate analog signals. At high speed, all boards are analog, and it takes careful engineering to make them digital instead.

 

If your PCB fails at low temperature for unknown reasons, this may help. As silicon gets colder, the internal resistance drops, and output transistions become faster. Signal crosstalk and ringing will be worse at low temperature and high voltage. For a worst case test, increase the operating voltage to the upper tolerance limit, and cool the product to the minimum operating temperature.

 

If one unit works at worst case, this does not mean there are no signal integrity problems with the design. Sometimes the problems are not noticed until many units have been built and field returns begin. The engineering work is not done until every interconnect has been examined with an oscilloscope and tweaked. Fortunately the signal integrity problems are very obvious at room temperature with a good oscilloscope, but careful design starts with the circuit board.

PCB Stackup

 

As logic has become faster and faster, the circuit board itself has become the key component of high speed digital design. In the past, one could just route traces any way that was convenient, minimize the PCB layers to save money, and it would all work fine. Not so anymore. Spending some more money on terminations and extra board layers has become a wise investment. Much cheaper than customer returns and missed ship dates.

 

How many layers should your board have? Usually the answer is as few as possible, but minimizing the layers could be a disaster for the product. When using CMOS high speed digital devices, it will be necessary to locate series termination resistors as close as possible to the driving pins, and far away from the receiver pins. This puts most of the action on the surface layers, and will require a ground return current directly underneath them to contain the emissions and provide good clean signals. A board with components on both sides will then need four layers just to handle the surface connections. Add another for power distribution and another for clock distribution plus signal routing. Here is a minimal six layer stackup:

 

 

Layer

Layer Use

Notes

1

Components, with series termination resistors

 

Width of trace and distance to ground plane establishes board impedance.

2

Ground Plane

 

3

Clock distribution and signal routing

Embedded microstrip. Match impedance to surface layers to avoid reflections.

4

Power Plane

 

5

Ground Plane

 

6

Components, with series termination resistors

 

Width of trace and distance to ground plane establishes board impedance.

Table 2.1: Absolute minimum layer stackup for an MPC5200B design. More layers are probably needed to fit a dense board.

 

Best practice for clock distribution is on an internal layer bounded by ground planes on each side. This effectively places the clock in a coaxial cable, called an embedded microstrip. Such an arrangement will minimize radiated emissions, which also minimizes induced crosstalk onto other traces.

 

See reference 1 for some very detailed multilayer PCB best practices.