Vulkan规范：第八章 8.2 ~ 8.3

8.2. 着色器的执行

在管线的每一个阶段，对着色器的多次调用可能同时执行。 甚至，多个命令都调用的单个着色器也可以同时执行。 调用同一个着色器类型所产生的相对执行顺序也是未知的。 应用程序绘制命令或者分发命令产生的图元的顺序和着色器调用完成的顺序也可能不一致。 然而，片元着色器输出到附件依栅格化顺序。

不同着色器类型调用的相对顺序基本上是未定义的。 然而，当调用的着色器的输入是前一个管线阶段的输出时，可以保证前一个阶段在产生所有必需的输入信息之前已经完成了。

8.3. 着色器内存访问顺序

着色器读取或者写入图像或缓冲区的顺序基本上是未定义的。 对于一些着色器类型（顶点、细分求值和某些情况下的片元着色器），甚至是可能进行加载和存储的着色器调用的次数也是未定义的。

尤其是以下规则应用时：

• 对于每一个不同的顶点，Vertex 和 tessellation evaluation 着色器将被至少调用一次。

• Fragment 着色器将被调用0次或者多次。

• 同类型的着色器的相对调用顺序是未定义的。 A store issued by a shader when working on primitive B might complete prior to a store for primitive A, even if primitive A is specified prior to primitive B. This applies even to fragment shaders; while fragment shader outputs are always written to the framebuffer in rasterization order, stores executed by fragment shader invocations are not.

• 不同类型着色器程序的相对调用顺序基本上是未定义的。

注意

上述的对于着色器调用的顺序的限制形成了在一系列的不可能实现的图元上着色器调用之间的同步。 For example, having one invocation poll memory written by another invocation assumes that the other invocation has been launched and will complete its writes in finite time.

Stores issued to different memory locations within a single shader invocation may not be visible to other invocations, or may not become visible in the order they were performed.

The OpMemoryBarrier instruction can be used to provide stronger ordering of reads and writes performed by a single invocation. OpMemoryBarrier guarantees that any memory transactions issued by the shader invocation prior to the instruction complete prior to the memory transactions issued after the instruction. Memory barriers are needed for algorithms that require multiple invocations to access the same memory and require the operations to be performed in a partially-defined relative order. For example, if one shader invocation does a series of writes, followed by an OpMemoryBarrier instruction, followed by another write, then the results of the series of writes before the barrier become visible to other shader invocations at a time earlier or equal to when the results of the final write become visible to those invocations. In practice it means that another invocation that sees the results of the final write would also see the previous writes. Without the memory barrier, the final write may be visible before the previous writes.

Writes that are the result of shader stores through a variable decorated with Coherent automatically have available writes to the same buffer, buffer view, or image view made visible to them, and are themselves automatically made available to access by the same buffer, buffer view, or image view. Reads that are the result of shader loads through a variable decorated with Coherent automatically have available writes to the same buffer, buffer view, or image view made visible to them. The order that coherent writes to different locations become available is undefined, unless enforced by a memory barrier instruction or other memory dependency.

Example 1. 注意

显式的内存依赖仍然需要使用，来保证对其他缓冲区、缓冲区视图、图像视图的访问的可用性和可见性。

内置的内存事务指令可以用来对给定内存地址读取或者写作的原子性。 当多个着色器调用内置的原子函数互相之间按照未定义的顺序执行时，这些函数都对一个内存地址进行内存读写操作， 且保证没有其他的内存事务将在读写期间对潜在的内存写入。 原子操作像对Coherent变量一样，保证了读写操作的可用性和可见性。

Example 2. 注意

在同一份内存上不同资源描述符进行内存访问，甚至有Coherent修饰符或通过原子操作，也可能是没有良好定义的， 因为诸如图像布局或者资源归属（Synchronization and Cache Control一章中讲解）等原因。

注意

原子操作允许着色器使用共享全局地址作为互斥性或者作为计数器，或其他用途。