用VHDL编写1602源代码

 

 

用VHDL编写1602源代码

已经试过了的

 

 

 

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LCD1602 is
  Port ( CLK : in std_logic;  --状态机时钟信号，同时也是液晶时钟信号，其周期应该满足液晶数据的建立时间
  Reset:in std_logic; 
         LCD_RS : out std_logic; --寄存器选择信号
         LCD_RW : out std_logic; --液晶读写信号
         LCD_EN : out std_logic; --液晶时钟信号
         LCD_Data : out std_logic_vector(7 downto 0));  --液晶数据信号
end LCD1602;
architecture Behavioral of LCD1602 is
  type state is (set_dlnf,set_cursor,set_dcb,set_cgram,write_cgram,set_ddram,write_LCD_Data);
  signal Current_State:state;
  type ram1 is array(0 to 7) of std_logic_vector(7 downto 0);
constant cgram1:ram1:=(x"58",x"69",x"61",x"6f",x"70",x"61",x"6e",x"67");
--显示我的名字的汉语拼音，以及FPGA/CPLD study by MIAOSHANLIN
signal  CLK1    : std_logic;
signal  Clk_Out : std_logic;
signal  LCD_Clk : std_logic;
signal  m       :std_logic_vector(1 downto 0);
begin
  LCD_EN <=  Clk_Out ;
  LCD_RW <= '0' ; 
process(CLK)
variable n1:integer range 0 to 19999;
begin
if rising_edge(CLK) then
   if n1<19999 then
      n1:=n1+1;
   else
      n1:=0;
     Clk_Out<=not Clk_Out;
    end if;
end if;
end process;
LCD_Clk <= Clk_Out;
process(Clk_Out)
variable n2:integer range 0 to 499;
begin
if rising_edge(Clk_Out) then
   if n2<499 then
      n2:=n2+1;
   else
      n2:=0;
     Clk1<=not Clk1;
    end if;
end if;
end process;
process(Clk1)
variable n3:integer range 0 to 4;
begin
if rising_edge(Clk1) then
   n3:=n3+1;
      m<="00";
end if;
end process;
process(LCD_Clk,Current_State)            
  variable cnt1: std_logic_vector(4 downto 0);
  begin
 if rising_edge(LCD_Clk)then
      Current_State <= Current_State ;
      LCD_RS <= '0';
    case Current_State is
      when set_dlnf=>      --显示清屏
        cnt1:="00000";     
        LCD_Data<="00000001";
        Current_State<=set_cursor;
      when set_cursor=>    --设置显示模式
        LCD_Data<="00111000";
        Current_State<=set_dcb;
      when set_dcb=>    --设置开关及光标
        LCD_Data<="00001111";
        Current_State<=set_cgram;
      when set_cgram=>    --设置光标
        LCD_Data<="00000110";
        Current_State<=write_cgram;
      when write_cgram=>       --读数据开始
        LCD_RS<='1';
     if m="00" then
        LCD_Data<=cgram1(conv_integer(cnt1));
     end if;
        Current_State<=set_ddram;
      when set_ddram=> 
    if cnt1<"11110" then
       cnt1:=cnt1+1;
    else
       cnt1:="00000";
    end if;
    if cnt1<="01111" then
       LCD_Data<="10000000"+cnt1;--80H
    else
       LCD_Data<="11000000"+cnt1-"10000";--80H
    end if;
       Current_State<=write_LCD_Data;
    when write_LCD_Data=>  
      LCD_Data<="00000000";
      Current_State<=set_cursor;
    when others => null;
    end case;
  end if;
end process;
end Behavioral;