使用风格1的信号发生器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity zhuantaiji is
    Port ( clk : in std_logic;
           wave : out std_logic := '0');
--           reset : in std_logic);
end zhuantaiji;

architecture Behavioral of zhuantaiji is
 type state is(state_init,state0, state1, state2,state3,state4,state5,state6);
 signal pr_state : state := state_init;  --为什么此处定义为信号
begin
-- pr_state <= state0;
-- wave <= '0';
 process (clk)
 begin
  case pr_state is
  when state_init =>
    if(clk='1') then
     wave <= '0';
     pr_state <= state0;
    end if;
   when state0 =>
    if(clk='1') then
     wave <= '1';
     pr_state <= state1;
    end if;
      when state1 =>
    if(clk = '1') then
     wave <= '0';
     pr_state <= state2;
    end if;
   when state2 =>
    if(clk = '1') then
     wave <= '1';
     pr_state <= state3;
    end if;
   when state3 =>
    if(clk = '1') then
     wave <= '1';
     pr_state <= state4;
    end if;
   when state4 =>
    if(clk = '1') then
     wave <= '1';
     pr_state <= state5;
    end if;
   when state5 =>
    if(clk = '1') then
     wave <= '0';
     pr_state <= state6;
    end if;
   when state6 =>
    if(clk = '1') then
     wave <= '0';
    -- pr_state <= state7;
    end if;
  -- when state7 =>
  --  if(clk = '1') then
  --   wave <= 0;
  --   pr_state <= state2;
  --  end if;
  end case;
 end process;
end Behavioral;