Sequential Y86 Implementations Part I ISA

每条指令都涉及到了很多个操作，所以现在就是要把这些指令的执行步骤统一起来，让所有的指令都按照统一的顺序来执行。

We organize them in a particular
sequence of stages, attempting to make all instructions follow a uniform sequence, even though the instructions
differ greatly in their actions.

 

 

Fetch: The fetch stage reads the bytes of an instruction from memory, using the program counter
(PC) as the memory address. From the instruction it extracts the two four-bit portions
of the instruction specifier byte, referred to as icode (the instruction code) and ifun (the
instruction function). It possibly fetches a register specifier byte, giving one or both of
the register operand specifiers rA and rB. It also possibly fetches a four-byte constant
word valC. It computes valP to be the address of the instruction following the current
one in sequential order. That is, valP equals the value of the PC plus the length of the
fetched instruction.

Decode: The decode stage reads up to two operands from the register file, giving values valA
and/or valB. Typically, it reads the registers designated by instruction fields rA and rB,
but for some instructions it reads register %esp.

Execute: In the execute stage, the arithmetic/logic unit (ALU) either performs the operation specified
by the instruction (according to the value of ifun), computes the effective address
of a memory reference, or increments or decrements the stack pointer. We refer to the
resulting value as valE. The condition codes are possibly set. For a jump instruction,
the stage tests the condition codes and branch condition (given by ifun) to see whether
or not the branch should be taken.

Memory: The memory stage may write data to memory, or it may read data from memory. We
refer to the value read as valM.

Write back: The write-back stage writes up to two results to the register file.

PC update: The PC is set to the address of the next instruction.

 

下面的图标详细描述了如何将这些指令分解后，按照统一的步骤来执行。