Loop filter calculation

Due to its low cost and low noise, it is desirable to employ a simple passive loop filter. A typical loop filter configuration can be seen in figure 14. 

 

The complete structure of the loop filter creates a fourth order loop (third order filter, the extra pole is created by the nature of the PLL). The components R0 and C0 represent the core of the loop filter, whereby the other components, C1, and the cascaded low pass R2 and C2, are employed to further enhance the system performance by adding higher order attenuation. The low pass filter may be omitted in many applications. In the optimisation of any PLL frequency synthesiser, there are three main considerations. Each factor has an influence on the selection of the loop bandwidth. The first factor is the selection of maximum available loop bandwidth to achieve minimum hopping time between two frequencies (for a channelised system). The second is the selection of minimum loop bandwidth for maximum suppression of reference sidebands in the output frequency spectrum. The third is the optimum selection of loop bandwidth for the minimum phase noise generated by the PLL. As the order of the loop increases the calculation of the loop filter components becomes cumbersome. In the following calculation method only the components R0 and C0 are generated from a theoretical approach, C1 is generated by a simple rule of thumb, and the low pass filter can be dimensioned to have a 3dB cutoff approximately a decade away from that of the loop bandwidth. 

First of all the designer must specify his system. This example assumes a channelised system of which locking time is the most critical. This is applicable to any FDMA/TDMA based radio standard. Specification of hopping time requires the definition of three parameters: 

• f_a (Hz) - frequency accuracy to desired frequency, i.e. how close the carrier must be to the desired frequency when hopping time is measured. 
• f_step (Hz) - frequency hopping step, taken from the lowest frequency required in the radio system to the highest required. 
• T (s) - hopping time, the maximum allowable time taken to switch between the channels farthest apart. As a rule of thumb, the highest lock speed achievable with conventional, i.e. non-fractional-N dual modulus systems is around 300microseconds. 

Taking E-GSM as an example, let FA =1kHz, f_step =880-960=80MHz and T=450ms 
Two parameters can be extracted from data supplied by the manufacturers of the components used: 

• K_v (Hz/V) - the conversion gain of the VCO employed. 
• I_cp (mA) - the DC charge pump current as measured at the output. Measurement conditions are usually specified as being the current drawn to ground or supply when the voltage on the charge pump output is held at midrail. 

If the charge pump currents are not equal, then the complete gain is calculated by adding the modulus of the positive source to that of the negative source and dividing by two. 

The channel spacing of the system must also be selected. This implies also the maximum frequency at which the phase detector can resolve phase differences between the two signals. It is desirable to make the phase detector operate at this frequency as, the higher the reference frequency, the lower the phase noise that will be generated on the carrier, furthermore no reference spurious will be generated within the loop bandwidth. When the channel spacing is decided, the mean N divider ratio can be calculated. Taking the approximate midband frequency, and dividing by the channel spacing results in the average N counter setting. For example...

 E-GSM band, bottom channel, 880MHz, top channel 960MHz, midband 920MHz. The IF must then be subtracted (for low side injection) from this frequency 920MHz-246MHz = 674MHz. Channel spacing 200KHz, 

N = 674 X 10 ⁶ /200 X 10 ³ 

N = 3370. 

In this case N represents the combined N (programmable divider) and P (prescaler) divide ratios. It doesn't matter if the resulting number is not a factor of the smallest prescaler dividing ratio, as the exact division ratios are taken care of by the dual modulus control logic. 

Now we come to our first calculation, the natural frequency of the loop. 

The following formula can be used to calculate f_n :-

 f_n = (-1/(2p*T*z)).ln(FA /f_step ). 

Where z is the damping factor of the loop. For this calculation, damping factor is chosen as 0.7. For a theoretical derivation of such a formula set, see the recommended texts listed at the end of this section. Subsequent to the calculation of f_n , the component value can be calculated as follows:-

 C0= I_cp *kV /(N(2p f_n )²) 

R0 = Ö(N/(I_cp kV C0))2z 

C2 can be approximated as C0/10. 

If a more accurate calculation is required of the full 3rd or 4th order loop then computer methods should be employed.