u-boot-1.1.4移植到pxa255板子上所做的修改
来源：互联网 发布：辐射4 卡顿优化 编辑：程序博客网 时间：2024/06/05 19:36
u-boot-1.1.4_new/board/lubbock/lowlevel_init.S
/*Enable all debug functionality */
movr0,#0x80000000
mcrp14,0,r0,c10,c0,0 /* dcsr */
#endif
+ /*Loading kernel image*/
+ ldr r4, =KERNEL_SRAM_BASE
+ ldr r5, =KERNEL_DRAM_BASE
+ ldr r6, =KERNEL_MAX_SIZE
+ add r6, r6, r4
+repeat1:
+ ldmia r4!, {r0-r3, r7-r10}
+ stmia r5!, {r0-r3, r7-r10}
+ cmp r4, r6
+ blt repeat1
+
/* ---------------------------------------------------------------- */
/* End lowlevel_init */
/* ---------------------------------------------------------------- */
endlowlevel_init:
mov pc, lr
u-boot-1.1.4/drivers/cs8900.c
#ifdef CONFIG_DRIVER_CS8900
+void MemSet(void *dest, char c, int len){
+ char *s=dest;
+ char *limit = (char *)dest+len;
+
+ while (s < limit) *s++ = c;
+ } // MemSet
+
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#undef DEBUG
@@ -64,13 +71,17 @@
c = CS8900_BUS16_1;
c = CS8900_BUS16_0;
+ MemSet((char *)0x04000000, 0x0, 2);
CS8900_PPTR = regno;
return (unsigned short) CS8900_PDATA;
}
#endif
+
+
static unsigned short get_reg (int regno)
{
+ MemSet((char *)0x04000000, 0x0, 2);
CS8900_PPTR = regno;
return (unsigned short) CS8900_PDATA;
}
@@ -78,6 +89,7 @@
static void put_reg (int regno, unsigned short val)
{
+ MemSet((char *)0x04000000, 0x0, 2);
CS8900_PPTR = regno;
CS8900_PDATA = val;
}
u-boot-1.1.4/include/configs/lubbock.h
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#define BOARD_LATE_INIT 1
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_PXA250 1 //cpu
+#define CONFIG_XSBASE 1 //
+#define KERNEL_SRAM_BASE 0x000C0000 //lowlevel_init.sпںʱõ
+#define KERNEL_DRAM_BASE 0xA0008000
+#define KERNEL_MAX_SIZE 0x00200000
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900 1 //֧cs8900
+#define CS8900_BUS16 1
+#define CS8900_BASE 0x04000300
+#define RTC 1
+#define CCCR_VALUE 0x00000161
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_JFFS2)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 3
+/*#define CONFIG_ETHADDR 08:00:3e:21:c7:f7*/
+#define CONFIG_ETHADDR 15:14:36:18:8A:11 //
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.0.10
+#define CONFIG_SERVERIP 192.168.0.1
+#define CONFIG_BOOTCOMMAND "go 0xa0008000" //bootloaderԶģʽʱĬеʾڴa0008000ĵطںˡ
+#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS0,115200"
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_TIMESTAMP
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER 1
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CFG_LONGHELP /* undef to save memory */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT "leibo$ " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_DEVICE_NULLDEV 1
+
+#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */
+
+#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED 0x00000161 /* set core clock to 400/200/100 MHz */
+//cpuƵʣڴƵʵֵ
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_MMC_BASE 0xF0000000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
+#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
+#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
+
+#define CFG_DRAM_BASE 0xa0000000
+#define CFG_DRAM_SIZE 0x04000000
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+#define FPGA_REGS_BASE_PHYSICAL 0x08000000
+
+/*
+ * GPIO settings //οemdoorӵֵ
+ */
+#define CFG_GPSR0_VAL 0x00408030
+#define CFG_GPSR1_VAL 0x00BFA882
+#define CFG_GPSR2_VAL 0x0001C000
+#define CFG_GPCR0_VAL 0xC0031100
+#define CFG_GPCR1_VAL 0xFC400300
+#define CFG_GPCR2_VAL 0x00003FFF
+#define CFG_GPDR0_VAL 0xC0439330
+#define CFG_GPDR1_VAL 0xFCFFAB82
+#define CFG_GPDR2_VAL 0x0001FFFF
+#define CFG_GAFR0_L_VAL 0x80000000
+#define CFG_GAFR0_U_VAL 0xA5000010
+#define CFG_GAFR1_L_VAL 0x60008018
+#define CFG_GAFR1_U_VAL 0xAAA5AAAA
+#define CFG_GAFR2_L_VAL 0xAAA0000A
+#define CFG_GAFR2_U_VAL 0x00000002
+
+
+
+#define CFG_PSSR_VAL 0x00000030
+
+/*
+ * Memory settings
+ */
+#define CFG_MSC0_VAL 0x7ff87ff0
+#define CFG_MSC1_VAL 0x12BC5554
+#define CFG_MSC2_VAL 0x7FF87FF1
+#define CFG_MDCNFG_VAL 0x00001AC9
+#define CFG_MDREFR_VAL 0x000BC018
+#define CFG_MDMRS_VAL 0x00000000
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL 0x00000000
+#define CFG_MCMEM0_VAL 0x00010504
+#define CFG_MCMEM1_VAL 0x00010504
+#define CFG_MCATT0_VAL 0x00010504
+#define CFG_MCATT1_VAL 0x00010504
+#define CFG_MCIO0_VAL 0x00004715
+#define CFG_MCIO1_VAL 0x00004715
+
+#define _LED 0x08000010
+#define LED_BLANK 0x08000040
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+//ϵflashֻ32Mѡ1Ϳ
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
+
+/* NOTE: many default partitioning schemes assume the kernel starts at the
+ * second sector, not an environment. You have been warned!
+ */
+#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
+#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16)
+
+
+/*
+ * FPGA Offsets
+ */
+#define WHOAMI_OFFSET 0x00
+#define HEXLED_OFFSET 0x10
+#define BLANKLED_OFFSET 0x40
+#define DISCRETELED_OFFSET 0x40
+#define CNFG_SWITCHES_OFFSET 0x50
+#define USER_SWITCHES_OFFSET 0x60
+#define MISC_WR_OFFSET 0x80
+#define MISC_RD_OFFSET 0x90
+#define INT_MASK_OFFSET 0xC0
+#define INT_CLEAR_OFFSET 0xD0
+#define GP_OFFSET 0x100
+
+#endif /* __CONFIG_H */
+
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