CPLD 八段数码管时钟显示的VHDL实现

--/*******************************************************************
-- *
-- *    DESCRIPTION: UART transmitter module.
-- *
-- *    AUTHOR:
-- *
-- *    HISTORY:
-- *
-- *******************************************************************/

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY Led_Segment IS
PORT (clk,reset : IN std_logic;
   led_en : OUT std_logic_vector(3 downto 0);
   clk_out  : OUT std_logic;
   led  : OUT std_logic_vector(3 downto 0);
   Seg_data : OUT std_logic_vector(6 downto 0);
   dot  : OUT std_logic);
END Led_Segment;

ARCHITECTURE behave OF Led_Segment IS
 SIGNAL clk_out_s : std_logic;
 SIGNAL led_en_s : std_logic_vector(3 downto 0);
 SIGNAL clk_led_en: std_logic;
 SIGNAL clk_s_re: std_logic;
 SIGNAL led_test : std_logic_vector(3 downto 0);
 SIGNAL Seg_reg : std_logic_vector(6 downto 0);
 CONSTANT CLK_DIV_RANGE  :integer := 7;
 CONSTANT CLK_DIV_C   :integer := 7;
 CONSTANT CLK_DIV_LED_RANGE :integer := 2047;
 CONSTANT CLK_DIV_LED_C  :integer := 1562;
 CONSTANT CLK_DIV_S_RANGE  :integer := 127;
 CONSTANT CLK_DIV_S_C   :integer := 99;
 SIGNAL s_1  :std_logic_vector(3 downto 0);
 SIGNAL s_10 :std_logic_vector(3 downto 0);
 SIGNAL m_1  :std_logic_vector(3 downto 0);
 SIGNAL m_10 :std_logic_vector(3 downto 0);
 SIGNAL data :std_logic_vector(3 downto 0);
-- SUBTYPE word is std_logic_vector(7 downto 0);
-- TYPE memory is array (0 to 3) of word;
-- SIGNAL led_data:memory;
BEGIN

-- led <= led_test;
 Seg_data <= Seg_reg;
 clk_out_gen : PROCESS (clk)
 VARIABLE clk_div : INTEGER RANGE 0 to CLK_DIV_RANGE;
 BEGIN
  if(reset ='0') then
   clk_div := 0;
  elsif(rising_edge(clk))then
   if(clk_div = CLK_DIV_C)then    --10000000/16
    clk_div := 0;
    clk_out_s <= not clk_out_s;
   else
    clk_div := clk_div + 1;
   end if;
  end if;
 END PROCESS;
-- clk_out <= clk_out_s;
 
 
 process(clk_out_s,reset)
 VARIABLE clk_led : INTEGER RANGE 0 to CLK_DIV_LED_RANGE;
 begin
  if(reset ='0') then
   clk_led := 0;
  elsif(rising_edge(clk_out_s)) then
   if(clk_led = CLK_DIV_LED_C) then
    clk_led := 0;
    clk_led_en <= not clk_led_en;   --the cycle is 10ms
   else
    clk_led := clk_led + 1;
   end if;
  end if;
 end process;
 
 process(clk_led_en,reset)
 VARIABLE clk_div_s : INTEGER RANGE 0 to CLK_DIV_S_RANGE;
 begin
  if(reset = '0')then
   clk_div_s := 0;
  elsif(rising_edge(clk_led_en))then
   if(clk_div_s = CLK_DIV_S_C) then
    clk_div_s := 0;
    clk_s_re <= not clk_s_re;
   else
    clk_div_s := clk_div_s + 1;
   end if;
  end if;
 end process;
 clk_out <= clk_s_re;
 
 process(clk_led_en,reset)
 begin
  if(reset ='0') then
   led_en_s <= "0100";
  elsif(rising_edge(clk_led_en)) then
    led_en_s(3) <= led_en_s(2);
    led_en_s(2) <= led_en_s(1);
    led_en_s(1) <= led_en_s(0);
    led_en_s(0) <= led_en_s(3);
  end if;
 end process;
 
 process(clk_out_s,reset)
 begin
  if(reset = '0')then
   data <= "0000";
  elsif rising_edge(clk_out_s) then
   case led_en_s is
   when "0001" =>
    data <= s_1;
   when "0010" =>
    data <= s_10;
   when "0100" =>
    data <= m_1;
   when others =>
    data <= m_10;
   end case;
  end if;
 end process;

 process(clk_out_s,reset)
 begin
  if(reset = '0')then
   Seg_reg <= "ZZZZZZZ";
  elsif rising_edge(clk_out_s) then
   case data is
   when "0001" =>
    Seg_reg <= "0000110";
   when "0010" =>
    Seg_reg <= "1011011";
   when "0011" =>
    Seg_reg <= "1001111";
   when "0100" =>
    Seg_reg <= "1100110";
   when "0101" =>
    Seg_reg <= "1101101";
   when "0110" =>
    Seg_reg <= "1111101";
   when "0111" =>
    Seg_reg <= "0000111";
   when "1000" =>
    Seg_reg <= "1111111";
   when "1001" =>
    Seg_reg <= "1101111";
   when others =>
    Seg_reg <= "0111111";
   end case;
  end if;
 end process;
 
 process(clk_out_s)
 begin
  if(rising_edge(clk_out_s)) then
   if(led_en_s = "0100")then
    dot <= clk_s_re;
   else
    dot <= '0';
   end if;
  end if;
 end process;
 
 process(clk_s_re,reset)
 begin
  if(reset = '0') then
   s_1 <= "0000";
  elsif(clk_s_re'event and clk_s_re = '1')then
   if(s_1 = "1001")then
    s_1 <= "0000";
   else
    s_1 <= s_1 + 1;
   end if;
  end if;
 end process;
 
 process(clk_s_re,reset)
 begin
  if(reset = '0')then
   s_10 <= "0000";
  elsif(clk_s_re'event and clk_s_re = '1')then
   if(s_1 = "1001") then
    if(s_10 = "0101") then
     s_10 <= "0000";
    else
     s_10 <= s_10 + 1;
    end if;
   end if;
  end if;
 end process;

 process(clk_s_re,reset)
 begin
  if(reset = '0')then
   m_1 <= "0000";
  elsif(clk_s_re'event and clk_s_re = '1')then
   if(s_10 = "0101" and s_1 = "1001") then
    if(m_1 = "1001") then
     m_1 <= "0000";
    else
     m_1 <= m_1 + 1;
    end if;
   end if;
  end if;
 end process;
 
 process(clk_s_re,reset)
 begin
  if(reset = '0')then
   m_10 <= "0000";
  elsif(clk_s_re'event and clk_s_re = '1')then
   if(m_1 = "1001" and s_10 = "0101" and s_1 = "1001") then
    if(m_10 = "0101") then
     m_10 <= "0000";
    else
     m_10 <= m_10 + 1;
    end if;
   end if;
  end if;
 end process;
 led_en <= led_en_s;
END behave;