宏模块的简单使用

简单计数移向模块

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;   --invold '+'  '-'
use ieee.std_logic_arith.all;      --  invold * mul   unsigned

ENTITY   phase3   IS
 PORT(  wave1,wave2,clk  :IN STD_LOGIC;
            en:out STD_LOGIC;            
            choose:out std_logic_vector(1 downto 0);  
            phase:out std_logic_vector(15 downto 0)
                                                          );
END phase3 ;

ARCHITECTURE   behv  OF   phase3     IS

SIGNAL c0   : std_logic;
SIGNAL locked   : std_logic;

SIGNAL  denom  :  STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL  numer  :  STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL  quotient :  STD_LOGIC_VECTOR (29 DOWNTO 0);

SIGNAL  quo      :  STD_LOGIC_VECTOR (29 DOWNTO 0);  

SIGNAL  dataa  :  STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL  result  :  STD_LOGIC_VECTOR (41 DOWNTO 0);
      
SIGNAL cout   : std_logic;

SIGNAL save1   : std_logic:='0';
SIGNAL save2   : std_logic:='0';

SIGNAL  cnt    : integer:=0;
SIGNAL  cnt1    : integer:=0;
SIGNAL  cnt2    : integer:=0;

signal temp,temp3,temp2,temp1: std_logic_vector(11 downto 0);
SIGNAL  num  :  STD_LOGIC_VECTOR (11 DOWNTO 0);

signal count,count1,count2,count3,count4: std_logic_vector(3 downto 0);
signal data: std_logic_vector(15 downto 0);  

component pll IS
 PORT
 (
  inclk0  : IN STD_LOGIC  := '0';
  c0      : OUT STD_LOGIC ;
  locked  : OUT STD_LOGIC
 );
END component;

component div IS
 PORT
 (
  clock  : IN STD_LOGIC ;
  denom  : IN STD_LOGIC_VECTOR (29 DOWNTO 0);
  numer  : IN STD_LOGIC_VECTOR (29 DOWNTO 0);
  quotient : OUT STD_LOGIC_VECTOR (29 DOWNTO 0);
  remain  : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
 );
END component;

component div10 IS
 PORT
 (
  clock  : IN STD_LOGIC ;
  denom  : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
  numer  : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
  quotient  : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
  remain  : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
 );
END component;

component mul IS
 PORT
 (
  clock  : IN STD_LOGIC ;
  dataa  : IN STD_LOGIC_VECTOR (29 DOWNTO 0);
  result  : OUT STD_LOGIC_VECTOR (41 DOWNTO 0)
 );
END component;

BEGIN

pttttt: pll port map (clk,c0,locked);

PROCESS(clk)  --fen  pin; 
variable  i : integer range 0 to 75000000;  
BEGIN

if locked='1' then

  if i=75000000 then
  i:=0;
  cout<='1';
  elsif clk'event and clk='1' then
  i:=i+1;
   if i=37500000 then
   cout<='0';
   end if;
  end if;
else null;
end if;
END PROCESS;

p1:PROCESS(wave1,wave2 ,c0  )
BEGIN
if locked='1' then
 if c0'event and c0='1' then    
    cnt<=cnt+1;
   
   if (save2 xor wave2)='1' then
  save2<=wave2;
  if wave2='1' then
    cnt2<=cnt;
    cnt<=1;
  else null;
  end if;
    else null;
    end if;
  
   if (save1 xor wave1)='1' then
  save1<=wave1;
  if wave1='1' then
    cnt1<=cnt;     
  else null;
  end if;
    else null;
    end if;
 else null;
 end if;    
else null;
end if;
END PROCESS;

pmul:mul port map(clk,dataa,result);
pdiv:div port map(clk,denom,numer,quotient );
pdiv10_1: div10 port map(clk,"1010",num,temp,count );

p3:PROCESS
variable state:integer :=0;
BEGIN
wait until clk'event and clk = '1';
   state := state + 1;  
  case state is
   when 100=>  dataa<=conv_std_logic_vector(cnt1,30);
   when 800=>
      numer<=result(29 downto 0);
                        denom<=conv_std_logic_vector(cnt2,30);
   when 1600=> quo<=quotient;            
      when 2000 => num<=quo(11 downto 0);
   when 2700=> temp3<=temp;
       data(3 downto 0)<=count;
   when 2800=> num<=temp3;
   when 3500=> temp2<=temp;
       data(7 downto 4)<=count;
   when 3700=> num<=temp2;
   when 4500=> temp1<=temp;
       data(11 downto 8)<=count;
   when 4700=>data(15 downto 12)<=temp1(3 downto 0);   
   when 74999999=>state:=0;
   
   when others=>NULL;
  end case; 
END PROCESS;

process (cout,count1,count2,count3,count4)

begin
if cout'event and cout='0' then
    choose<="01";
 phase<=data;
else null;
end if;
end process;
en<=cout;
END ;