乒乓球游戏源程序

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-- Company:
-- Engineer:
--
-- Create Date:    13:27:54 08/18/2010
-- Design Name:
-- Module Name:    pingpang - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pingpang is
    Port ( co : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           left : in  STD_LOGIC;
           right : in  STD_LOGIC;
           wavex : out  STD_LOGIC;
           wavey : out  STD_LOGIC;
           leftlight : out  STD_LOGIC;
     rightlight : out  STD_LOGIC;
     sel:    out std_logic_vector(3 downto 0);
     led :out std_logic_vector(6 downto 0));
end pingpang;

architecture Behavioral of pingpang is

SIGNAL  i : std_logic_vector(11 downto 0):=(others=>'0');  --2500
SIGNAL  j : std_logic_vector(14 downto 0):="000000001100100"; --100 --20 099
SIGNAL  ym : std_logic_vector(11 downto 0):=(others=>'0');  --2500
SIGNAL  ymy : std_logic_vector(11 downto 0):=(others=>'0');  --2500
component mul50 IS
 port (
 clk: IN std_logic;
 a: IN std_logic_VECTOR(5 downto 0);
 b: IN std_logic_VECTOR(5 downto 0);
 p: OUT std_logic_VECTOR(11 downto 0));
END component;
SIGNAL  da  :  STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL  db  :  STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL  result:  STD_LOGIC_VECTOR (11 DOWNTO 0);

SIGNAL  mn  :  STD_LOGIC_VECTOR (14 DOWNTO 0);
SIGNAL  mny  :  STD_LOGIC_VECTOR (12 DOWNTO 0);
component div IS
 port (
 clk: IN std_logic;
 dividend: IN std_logic_VECTOR(12 downto 0);
 divisor: IN std_logic_VECTOR(6 downto 0);
 quotient: OUT std_logic_VECTOR(12 downto 0);
 remainder: OUT std_logic_VECTOR(6 downto 0);
 rfd: OUT std_logic);
END  component;
SIGNAL  dom  :  STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL  num  :  STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL  quo   : STD_LOGIC_VECTOR (12 DOWNTO 0);

signal clk ,clkled:std_logic;
signal countleft,countright:std_logic_vector(1 downto 0);
signal leok:std_logic_vector(1 downto 0):="00";
signal riok:std_logic_vector(1 downto 0):="00";

signal power :std_logic:='0';
signal righth,rightl,lefth,leftl:std_logic_vector(3 downto 0):="0000";
signal ledrl,ledll:std_logic_vector(6 downto 0):="1111110";  --0
signal ledrh,ledlh:std_logic_vector(6 downto 0):="1111110";  --0
signal rest,rs:std_logic;
signal ll,rl:std_logic;
signal se:std_logic_vector(3 downto 0);
signal leftlose,rightlose:std_logic;
BEGIN

PROCESS(co)
variable  p : integer range 0 to 4;
BEGIN
if p=4 then
   p:=0;
clk<='1';
elsif co'event and co='1' then
 p:=p+1;
 if p=2 then
 clk<='0';
 end if;
end if;
END PROCESS;

process(co)
variable lk:std_logic_vector(9 downto 0);
begin
if co'event and co='1' then
lk:=lk+1;
end if;
clkled<=lk(9);
end process;

pdiv: div port map(clk,num,dom,quo);  --2 clk
Pmul50: mul50 port map(clk,da,db,result);  --2 clk

process(rst,rightlose)
begin
if rst = '1' then
leftl<="0000";
lefth<="0000";
elsif (rightlose'event and rightlose='1') then
  leftl<=leftl+1;
  if leftl="1001" then
   leftl<="0000";
    if lefth="1001" then
     lefth<="0000";
    else lefth<=lefth+1;
    end if;
  end if;
end if;
end process;

process(rst,leftlose)
begin
if rst = '1' then
rightl<="0000";
righth<="0000";
elsif (leftlose'event and leftlose='1') then
  rightl<=rightl+1;
  if rightl="1001" then
   rightl<="0000";
    if righth="1001" then
     righth<="0000";
    else
    righth<=righth+1;
    end if;
  end if;
end if;
end process;
--
--leftlight <= not leftllose;
--rightlight <=not rightllose;
process
variable jx :std_logic_vector(14 downto 0) ;
variable xix:std_logic_vector(14 downto 0) ;
variable xixx:std_logic_vector(11 downto 0) ;
variable state: std_logic_vector(3 downto 0):=(others=>'0');
variable leftfollow:std_logic:='0';
variable rightfollow:std_logic:='0';
begin
wait until clk'event and clk='1';
rs<=rst or rest;

if rs='1' then
   i<=(others=>'0');
 j<="000000001100100";
 jx:=(others=>'0');
 rest<='0';    --rest <="0"
 state:=(others => '0');
 wavex<='0';
 wavey<='0';
 ymy<=(others => '0');
 mn<=(others => '0');
 xix:=(others=>'0');
 xixx:=(others=>'0');
 leftlose<='0';
 rightlose<='0';
 power<='0';
else
   if i=2500 then
    j<=j+1;
    i<=(others=>'0');
    wavey<='0';
    wavex<='1';
    if jx=20000 then
     jx:=(others=>'0');
    else 
     jx:=jx+1;
    end if;
   else
    i<=i+1;
    if i=xixx then
      wavex<='0';
    end if;
   end if; 
   if i=ymy then   
     if i=2500 then
     wavey<='0';
     else
     wavey<='1';
     end if;  
    end if;
   
    state:=i(11 downto 8); 
          case state is                 
    when "0000" => if j<=5099 then
          mn<=j;    
        
          end if;     
        if (j>5099 and j<=10099) then
         mn<=10099-j;
           leftlight<='1'; -- --leftlight off
         leok<="00";     --leok back "00"
         leftlose<='0';  --leftlose <= 0
        end if;
          if (j>10099 and j<=15099) then
           mn<=j-10000;
          end if;
          if (j>15099 and j<20099)  then
           mn<=20099-j;
          rightlight<='1';    -- --rightlight off
                          riok<="00";           --riok back "00"
          rightlose<='0';      --rightlose <= 0
                       end if;                  
          if j=20099 then
            j<="000000001100011";   --99
            mn<="000000001101100";--108
            jx:=(others=>'0');
          end if;

    when "0001"=>   if jx<=5000 then
         xix:=jx+5000;
       elsif jx<=15000 then
          xix:=15000-jx;
       else xix:=jx-15000;
       end if;
    when "0010"=> xixx:=xix(13 downto 2);    
    when "0011"=> if xix<=2 then
           xix:="000000000000010"; 
          end if;
    
    when "0101" => 
          mny<=mn(12 downto 0);
         
    when "0110" =>  dom<="1100100";--100
          num<=mny; 
    when "0111" => da<=quo(5 downto 0);                                                  
          db<=quo(5 downto 0);  
        
    when "1000"=> if power='1' then
                       ymy<=result; 
                 else ym<='0'&result(11 downto 1);
              ymy<=ym+1250;
         end if;
    when "1001"=>  if ymy<=2 then
          ymy<="000000000010";                    
          end if;
    when others => null;
    end case;
   

     if (jx>3750 and jx<5000 )then             --right hit the ball
     if right='1' then
      countright<="00";
     elsif countright<3  then
       countright<=countright+1;
     end if;
     
     if countright=2 then
       riok<=riok+1;
     end if;
    end if;
    
    if jx=5000 then    
       if  riok="00" then  
         rightlight<='0';            ----rightlight on  right hit the bal rose                
         rest<='1';           -- rest
         rightlose<='1';      --rightlose
       end if;
       if riok="01" then
          power<='0';
       end if;
       if  riok="10" then
        power<='1';          --high   ball
       end if;
    end if;
    if (jx>13750 and jx<15000 ) then    -- left hit the ball
       if left='1' then
       countleft<="00";
       elsif countleft<3  then
         countleft<=countleft+1;
       end if;
      
      if countleft=2 then
        leok<=leok+1;
      end if;
    end if; 
    
            if jx=15000 then
       if leok="00" then  
       leftlight<='0';            ----rightlight on  right hit the bal rose                
       rest<='1';           -- rest
       leftlose<='1';       --leftlose
       end if;
       if leok="01" then
                      power<='0';
      end if;
       if  leok="10" then
       power<='1';         --high ball
      end if;
            end if;

end if;  --rest
end process;

process
begin
wait until clkled'event and clkled='1';
      case rightl is
        when "0000"=> ledrl<="1111110";
  
    when "0001"=> ledrl<="0110000";
    when "0010"=> ledrl<="1101101";
    when "0011"=> ledrl<="1111001";
    when "0100"=> ledrl<="0110011";
    when "0101"=> ledrl<="1011011";
    when "0110"=> ledrl<="1011111";
    when "0111"=> ledrl<="1110000";
    when "1000"=> ledrl<="1111111";
    when "1001"=> ledrl<="1110011";
    when others => null;
   end case;
   case righth is
        when "0000"=> ledrh<="1111110";
    when "0001"=> ledrh<="0110000";
    when "0010"=> ledrh<="1101101";
    when "0011"=> ledrh<="1111001";
    when "0100"=> ledrh<="0110011";
    when "0101"=> ledrh<="1011011";
    when "0110"=> ledrh<="1011111";
    when "0111"=> ledrh<="1110000";
    when "1000"=> ledrh<="1111111";
    when "1001"=> ledrh<="1110011";
    when others => null;
   end case;
  
   case leftl is
        when "0000"=> ledll<="1111110";
    when "0001"=> ledll<="0110000";
    when "0010"=> ledll<="1101101";
    when "0011"=> ledll<="1111001";
    when "0100"=> ledll<="0110011";
    when "0101"=> ledll<="1011011";
    when "0110"=> ledll<="1011111";
    when "0111"=> ledll<="1110000";
    when "1000"=> ledll<="1111111";
    when "1001"=> ledll<="1110011";
    when others => null;
   end case;
   case lefth is
        when "0000"=> ledlh<="1111110";
    when "0001"=> ledlh<="0110000";
    when "0010"=> ledlh<="1101101";
    when "0011"=> ledlh<="1111001";
    when "0100"=> ledlh<="0110011";
    when "0101"=> ledlh<="1011011";
    when "0110"=> ledlh<="1011111";
    when "0111"=> ledlh<="1110000";
    when "1000"=> ledlh<="1111111";
    when "1001"=> ledlh<="1110011";
    when others => null;
   end case;
  
   case se is
   when "0001" => se<="0010";led<=ledlh;
   when "0010" => se<="0100";led<=ledll;
   when "0100" => se<="1000";led<=ledrh;
   when "1000" => se<="0001";led<=ledrl;
   when others => se<="0001";
     end case;
  sel<=se;
end process;
END ;