Address Disposition for Processor

Address Disposition for Processor

 

Address range

 

Conditions

Intel 5000P chipset Behavior

DOS

 

0 to 09FFFFh

Coherent Request to Main Memory.
Route to main memory according to Intel 5000P
chipset MCH.MIR registers. Apply Coherence Protocol

SMM/VGA

 

0A0000h to 0BFFFFh

详细见MCH SPEC

C and D BIOS
segments

 

0C0000h to 0DFFFFh and PAM=11

Non-coherent request to main memory. Rout to
appropriate FB-DIMM device according to Intel 5000P
chipset MCH.MIR registers.

 

Write to
0C0000h to 0DFFFFh and PAM=10

 

Read to
0C0000h to 0DFFFFh and PAM=01

 

Read to
0C0000h to 0DFFFFh and PAM=10

Issue request to ESI.

 

Write to
0C0000h to 0DFFFFh and PAM=01

 

0C0000h to 0DFFFFh and PAM=00

E and F BIOS
segments

 

0E0000h to 0FFFFFh and PAM=11

Non-coherent request to main memory. Rout to
appropriate FB-DIMM device according to Intel 5000P
Write to chipset MCH.MIR registers.

 

write to
0E0000h to 0FFFFFh and PAM=10

 

Read to
0E0000h to 0FFFFFh and PAM=01

 

Read to
0E0000h to 0FFFFFh and PAM=10

Issue request to ESI.

 

Write to
0E0000h to 0FFFFFh and PAM=01

 

0E0000h to 0FFFFFh and PAM=00

Low/Medium
Memory

 

10_0000 <= Addr < TOLM

Coherent request to main memory. Route to main
memory according to Intel 5000P chipset MCH.MIR
registers. Coherence protocol is applied.
Note: the extended SMRAM space is within this range

Extended
SMRAM Space

 

ESMMTOP-TSEG_SZ <= Addr <
ESMMTOP

Top of Extended SMM Space:

它的默认值和TLOM相同！

Low MMIO

 

TOLM <= Addr < FE00_0000 and
falls into a legal BASE/LIMIT range

Request to PCI Express based on <MBASE/MLIMIT and
PMBASE/PMLIMIT> registers

 

TOLM <= Addr < FE00_0000 and
not in a legal BASE/LIMIT range

Send to ESI to be master aborted.

PCI Express
MMCFG

 

HECBASE <= Addr <
HECBASE+256MB

Convert to a configuration access and route according
to the Configuration Access Disposition.

Intel 5000P
chipset specific

 

FE00_0000h to FEBF_FFFFh AND
valid Intel 5000P chipset memory
mapped register address plus AMB
targeted addresses

Issue configuration access to memory mapped register
inside Intel 5000P chipset or to the FB-DIMM based on
the context.

 

FE00_0000h to FEBF_FFFFh AND
(NOT a valid Intel 5000P chipset
memory mapped register address
or NOT a valid AMB targeted
address)

Send to ESI to be master aborted.

I/O APIC
registers

 

FEC0_0000 to FEC8_FFFFh

Non-coherent request to PCI Express or ESI based on
Table 4-4.

Intel
631xESB/632x
ESB I/O
Controller Hub
/ Intel
631xESB/632x
ESB I/O
Controller Hub
timers

 

FEC9_0000h to FED1_FFFF

Issue request to ESI.

High SMM

 

FEDA_0000h to FEDB_FFFF

详见MCH spec.

Interrupt

 

interrupt transaction to
FEE0_0000h to FEEF_FFFFh
(not really memory space)

Route to appropriate FSB(s).

 

memory transaction to
FEE0_0000h to FEEF_FFFFh

Send to ESI to be master aborted.

Firmware

 

FF00_0000h to FFFF_FFFFh

Issue request to ESI.

High Memory

 

1_0000_0000 to MIR[2].LIMIT
(max FF_FFFF_FFFF)

Coherent request to main memory. Route to main
memory according to Intel 5000P chipset MCH.MIR
registers. Coherence protocol is applied.

High MMIO

 

PMBU+PMBASE <= Addr <=
PMLU+PMLIMIT

Route request to appropriate PCI Express port

All others

 

All Others (subtractive decoding)

Issue request to ESI.

 

Intel 5000P Chipset MCH Memory Mapping Registers

Name

 Function

MIR[2:0]

 Memory Interleaving Registers (FB-DIMM Branch Interleaving)

AMIR[2:0]

 Scratch pad register for software to use related to memory interleaving. For example, software can write MMIO gap adjusted limits here to aid in subsequent memory RAS operations

PAM[6:0]

 Defines attributes for ranges in the C and D segments. Supports shadowing by routing reads and writes to memory of I/O

SMRAMC

SMM Control

EXSMRC, EXSMRAMC

 Extended SMM Control

EXSMRTOP

Top of extended SMM memory

BCTRL

Contains VGAEN and ISAEN for each PCI Express.

TOLM

 Top of low memory. Everything between TOLM and 4 GB will not be sent to memory.

HECBASE

 Base of the memory mapped configuration region that maps to all PCI Express registers

MBASE (dev 2-7)

Base address for memory mapped I/O to PCI Express ports 2 - 7

MLIMIT (dev 2-7)

 Limit address for memory mapped I/O to PCI Express ports 2 - 7

PMBASE (dev 2-7)

Base address for memory mapped I/O to prefetchable memory of PCI Express ports 2-71

PMLIMIT (dev 2-7)

Limit address for memory mapped I/O to prefetchable memory of PCI Express ports 2-7

PMBU (dev 2-7)

 Prefetchable Memory Base (Upper 32 bits) - Upper address bits to the base address of prefetchable memory space. If the prefetchable memory is below 4GB, this register will be set to all 0’s.

PMLU (dev 2-7)

Prefetchable Memory Limit (Upper 32 bits) - Upper address bits to the limit address of prefetchable memory space. If the prefetchable memory is below 4GB, this register will be set to all 0’s.

PCICMD (dev 2-7)

 MSE (Memory Space Enable) bit enables the memory and prefetchable ranges.