Verilog的关键字及意义（未完持续编辑中）

always

ifnone

rnmos

and

incdir

rpmos

assign//标记赋值

include

rtran

automatic

initial

rtranif0

begin

inout

rtranif1

buf

input//输入

scalared

bufif0

instance

showcancelled

bufif1

integer

signed

case

join

small

casex

large

specify

casez

liblist

specparam

cell

library

strong0

cmos

localparam

strong1

config

macromodule

supply0

deassign

medium

supply1

default

module

table

defparam

nand

task

design

negedge//下降沿

time

disable

nmos

tran

edge

nor

tranif0

else//相反

noshowcancelled

tranif1

end

not

tri

endcase

notif0

tri0

endconfig

notif1

tri1

endfunction

or

triand

endgenerate

output//输出

trior

endmodule

parameter

trireg

endprimitive

pmos

unsigned

endspecify

posedge//上升沿

use

endtable

primitive

vectored

endtask

pull0

wait

event

pull1

wand

for//循环

pulldown

weak0

force

pullup

weak1

forever

pulsestyle_onevent

while

fork

pulsestyle_ondetect

wire

function

rcmos

wor

generate

real

xnor

genvar

realtime

xor

highz0

reg//寄存器变量

highz1

release

if、、条件

repeat