zz spru976阅读心得

来源：互联网发布：易看小说cms 编辑：程序博客网时间：2024/05/08 16:10

版本信息： Literature Number: SPRU976 March 2006

SRIO 部件
1. LSU / MAU ： dio， doorbell, maintenance
2. TXU/ RXU : message
3. SERDES macro: serial --- parallel 转换
4. LSU & TXU 共用一个 4.5 kb buffer， MAU & RXU 共用一个 4.5 kb buffer，
SERDES
1. PLL —— used for the clock recovery circuitry， responsible for clock multiplication of a slow speed reference clock
2. To enable a receiver for deserialization, the ENRX bit of the associated SERDES_CFGRXn_CNTL registers (100h-10Ch) must be set high.
3. To enable a transmitter for serialization, the ENTX bit of the associated SERDES_CFGTXn_CNTL registers (110h-10Ch) must be set high.
DirectIO
1. Data Path
  1. transfer descriptors are written -->
  2. flow control status is queried. The unit examines the DESTID and PRIORITY fields of LSUn_REG4 to determine if that flow has been Xoffd. -->
  3. Additionally, the free buffer status of the TX FIFO is checked (based on the OutPortID register field). -->
  4. TX FIFO buffer has been allocated -->
  5. Data is moved from the shared TX buffer to the appropriate output TX FIFO in simple sequential order based on completion of the DMA bus transaction. -->
Messaging
1. CPPI is the protocol engine
2. 没有 read，但是有 response packet
3. Data Path
  1. Logical layer route ftype-11 and ftype-13 packet to CPPI. Rx FIFO --> CPPI buffer
  2. Mailbox mapper block examine mbox header field,
  3. Based on the mailbox and message length, the data is assigned memory addresses within memory.
  4. DMA transfer data buffer --> L2 Memory. Each message in memory will be represented by a buffer descriptor in the queue.
4. CPPI rules:
  1. · 每个buffer descriptor     对应一个   message                          (each buffer descriptor consists of 4 words or 16 bytes).
    
    · 多个片段的读写操作要求有连续的内存空间                        Contiguous memory space is required for multi-segment read and write operations.
    
                       – There are fixed buffer sizes (configured to handle the application's maximum message size).
    
    · 如果message 的大小大于已分配的buffer大小，返回错误       An ERROR response is sent if the RX message is too big for the allotted buffer space.
    
                       – ERROR responses are sent for all subsequent segments of that message.
    
    · An ERROR response is sent if the mailbox is not mapped, or if it is mapped to a non-existent queue.
    
    · An ERROR response is sent if the mailbox is mapped but the queue is not initialized (the head descriptor pointer is not written), or if the queue is disabled (due to a teardown).
    
    · An ERROR response is sent if the RX buffer descriptor queue has no empty buffers (there is an overflow) .
    
    · Out-of-order responses are allowed.
    
    · A RETRY response is issued to the first received segment of a multi-segment message when the RX queue is busy servicing another request.
    
                       – Subsequent RETRY responses may have to be sent for received pipeline segments or additional pipelined messages to the same queue.
    
    · In-order message reception for dedicated flows is mode programmable.
    
    · 每个被支持的同发的多片段 Rx 信息，需要一个 queue。      A queue is needed for each supported simultaneous multi-segment RX message.
    
    · A minimum of 1.25K bytes of SRAM (64 buffer descriptors) is supported.
    
    · The transmit source must be able to retry any given segment of a message.
    
    · ？？？？？？？？？？？？？？？？？？？？？DESTID is equal to port for TX operations, and the same DESTID is not accessible from multiple ports.
5. The DSP contains buffer description tables for each mailbox. These tables define a memory map and pointers for each mailbox.
  1. 每个邮箱有 buffer description tables（表），这些表定义了每个邮箱的 memory map 和指针。
6. Rx Operation
  1. Messages addressed to any of the 64 mailbox locations can be received on any of the RapidIO ports simultaneously. Packets are handled sequentially in order of receipt.
  2. Mailbox Mapper : directs the inbound messages to the appropriate queue based on a pre-programmed routing table, finally to the correct core
    1. SOURCEID, MSGLEN (the size indicates whether the message is segmented), MBOX, LETTER, and XMBOX fields
    2. There are 32 programmable look-up table entries for mapping mailboxes to queues.
    3. If a mailbox/letter is not supported or does not have a mapping table entry, the message is discarded and an ERROR response sent.
    4. the mask fields can be used to grant multiple mailbox/letter combinations access to a queue using the same table entry.
    5. single or multi-segment message mapping
      1. Single segment message mapping entries utilize all six bits of the mailbox and corresponding mask fields.
    6. Multi-segment entries uses only the 2 LSBs.
      1. The number of simultaneous supported multi-segment messages is determined by the number of dedicated RX queues as discussed further below. It is recommended to dedicate a multi-segment mapping entry for each supported simultaneous letter.
      2. Essentially, letter masks should be avoided for multi-segment mapping to reduce excessive retries. Note that it is possible to configure the table entries such that incoming single segment and multi-segment messages are directed to the same queue. To avoid this condition, properly program the mapping table entries.
    7. Packet Manager : maintains the RX DMA state of free and used data buffers within the memory space.
      1. It is suggested that one queue be dedicated to single segment messages and additional queues be dedicated to multi-segment messages.
      2. Each multi-segment message queue can support only one incoming message at a time.
  3. The queue mapping is programmable and must be configured after device reset.
  4. RX Queue Head Descriptor Pointer :
    - This field is the memory address for the first buffer descriptor in the channel receive queue.
    - This field is written by the DSP core to initiate queue receive operations and
    - is zeroed by the port when all free buffers have been used.
    - An error condition results if the DSP core writes this field when the current field value is nonzero.
    - The address must be 32-bit word aligned.
  5. RX Queue Completion Pointer
    - This field is the memory address for the receive queue completion pointer.
    - This register is written by the DSP core with the buffer descriptor address for the last buffer processed by the DSP core during interrupt processing.
    - The port uses the value written to determine if the interrupt should be de-asserted.
  6. Buffer Descriptor
    1. A RX buffer descriptor is a contiguous block of four 32-bit data words aligned on a 32-bit boundary.
    2. points to the corresponding data buffer in memory
    3. also points to the next buffer descriptor in the queue.
    4. As segments of a received message arrive, the msgseg field of each segment is monitored to detect the completion of the received message
    5. Once a full message is received, the OWNERSHIP bit is cleared in the packet's buffer descriptor to give control to the host. At this point, a host interrupt is issued.
    6. Interrupt
      1. On interrupt, the CPU processes the RX buffer queue, detecting received packets by the status of the OWNERSHIP bit in each buffer descriptor.
      2. The host processes the RX queue until it reaches a buffer descriptor with a set OWNERSHIP bit, or set EOQ bit.
      3. Once processing is complete, the host updates the RX DMA State Completion Pointer, allowing the peripheral to reuse the buffer.
    7. queue teardown
7. Tx Operation
  1. Tx buffer descriptor
    1. buffer descriptor queues that are assigned by the CPUs
    2. The queues are configured and initialized upon reset.
    3. A TX buffer descriptor is a contiguous block of four 32-bit data words aligned on a 32-bit boundary.
  2. Data Path
    1. When a CPU wants to send a message to an external RapidIO device, it writes the buffer descriptor information via the configuration bus into the SRAM.
    2. Upon completion of writing the buffer descriptor, the OWNERSHIP bit is set to give control to the peripheral.
    3. The CPU then writes the TX DMA State HDP register to initiate the queue transmit.
    4. Once the port controls the buffer descriptor, the DEST_ID field can be queried to determine flow control.
    5. The TX state machine begins by processing the current TX_Queue_Map(n).
      1. It will attempt to process the queue and number of buffer descriptors from that queue programmed in this mapping entry. Then it will move to TX_Queue_Map(n+1), followed by TX_Queue_Map(n+2) and so forth.
8. 软件操作
  1. Rx 方面操作
    1. 指定邮箱--queue 之间的映射，并指定那些ID 的邮件信息可以被发到该邮箱--queue
    2. 分配 buffer descriptor memory （可以是 CPPI RAM 或者 L2 RAM ）
    3. 把 buffer descriptors 连接起来（link list， next_descriptor_pointer ）
    4. 分配单片段、多片段的 buffer 到 queue （buffer_length）
    5. 分配 buffer descriptor 给 data buffer （buffer_pointer）
    6. 把 buffer 的控制权转移给 peripheral （设 ownership = 1 ）
    7. 配置、初始化 Rx queue
      1. 分配 Head Descriptor Pointer（HDP）给最多 16 个 queue （RX DMA State HDP）
    8. Port 开始调用 buffer （由 HDP 指定的），并将该 buffer 的 ownership 设为 0 。之后，写入 Completion Pointer, CP, RX DMA State CP 。然后，调用下一个 buffer。
    9. 当 CP 被写后，生成中断
    10. 中断处理
      1. 判断 ICSR bit，并处理相应的queue 直到 ownership = 1 or eoq = 1
      2. 把已处理的 buffer descriptor 的 ownership 设为 1
      3. 把已处理的 last buffer descriptor 的 CP 写入值。
      4. port 将 ICSR bit 清零（如果 CP 值等于 Rx DMA State CP register）
      5. reset interrupt pacing value
  2. Tx 方面操作
    1. 把 buffer descriptors 连接起来（link list， next_descriptor_pointer ）
    2. 分配 buffer descriptor 给 data buffer （buffer_pointer）
    3. CPU 将每个已使用的 buffer descriptors 写入值并且设 ownership = 1
    4. 指定 RIO 域： Dest_id, Pri, tt, Mailbox
    5. 设参数： PortID, Message_length
    6. Port starts queue transmit on CPU write to HDP for up to 16 queues - TX DMA State HDP
    7. port 处理相应的 queue 直到 ownership = 0 or next_descriptor_pointer = all 0s 。 Prot 把 eoq 设为 1 并向 HDP 写入全 0s。
    8. 当每个 packet transmission 完成后， port 把 ownership 设为0，并生成一个中断（通过将 last processed buffer descriptor address 写入 CP, TX DMA State CP 。
    9. 中断处理
      1. CPU 处理 buffer queue 并重用 buffer 。（ ownership = 0 ）
      2. CPU processes the queue until eoq = 1（到末尾） or ownership = 1（buffer正在被使用）
      3. CPU 判断所有 packet 都已经被发出了，如果：
        
        ownership = 0,
        
        eoq = 1,
        
        and next_descriptor_pointer = all 0s in last processed buffer descriptor
      4. CPU 通过写入 CP 值以表明中断处理完成。
      5. 该 CP 值会与 TX DMA State CP register 进行比较；如果相等，则中断被 de-assert
9. Messaging 相关 register
  1. 名称
    地址
    个数
    描述
    
    RXU_MAP_Ln
    0x0800
    32
    
    RXU_MAP_Hn
    0x0804
    32
Interrupt Conditions
1. 三种 CPU interrupt
  1. Error status: Event indicating that a run-time error was reached. The CPU should reset/resynchronize the peripheral.
  2. Critical error: Event indicating that a critical error state was reached. The CPU should reset the system.
  3. CPU servicing: Event indicating that the CPU should service the peripheral.
2. General Description
  1. RIO peripheral 可以触发几种 CPU 中断。
  2. 触发中断的只能是：
    1. RIO peripheral
    2. external PE
  3. Doorbell
    1. Each (info) bit can be assigned to any core as described by the Interrupt Condition Routing Registers.
    2. Additionally, each status bit is user-defined for the application.
  4. Messaging Interrupt
    1. Interrupts are generated by the peripheral after all segments of the messages are received and successfully transferred through the DMA bus with the write-with-response commands.
    2. Interrupt pacing is also implemented at the peripheral level to manage the interrupt rate,
3. Interrupt Condition Status and Clear Registers
  1. Interrupt Condition Status Register (ICSR): Status register that reflects the state of each condition that can trigger the interrupt.
  2. Interrupt Condition Clear Register (ICCR): Command register that allows each condition to be cleared.
  3. The CPU controls the clear register. The status register is readable by the CPU to determine the peripheral condition.
  4. Doorbell Interrupt
    1. These registers are used when the SRIO peripheral receives doorbell packets.
    2. The 16 ICS bits of each interrupt condition status register (ICSR) indicate the incoming doorbell information packet.
  5. CPPI Interrupt
    1. These interrupt condition registers are used when the SRIO peripheral receives and transmits data message packets.
    2. Each ICS bit corresponds to the interrupt for one of the buffer descriptor queues.
  6. LSU Interrupt
    1. These interrupt condition registers are used when the SRIO peripheral transmits direct I/O packets.
    2. each of the status and clear bits corresponds to a particular type of transaction interrupt condition for a particular LSU.
4. Interrupt Condition Routing Registers (ICRRs)
  1. The interrupt conditions are programmable to select the interrupt output that will be driven.
  2. Using the interrupt condition routing registers (ICRRs), software can independently route each interrupt request to any of the interrupt destinations supported by the device.
5. Interrupt Status Decode Registers (ISDR)
6. Interrupt Generation
  1. the physical interrupts are set only when the total number of set ICSR bits transitions from none to one or more.
  2. The peripheral is responsible for setting the correct bit within the ICSR.
  3. The ICRR register maps the pending interrupt request to the appropriate physical interrupt line.
  4. The corresponding CPU is interrupted and reads the ISDR and ICSR registers to determine the interrupt source and appropriate action.
7. Interrupt Pacing
  1. The rate at which an interrupt can be generated is controllable for each physical interrupt destination.
  2. The load value of the counter is written by the CPU into the appropriate interrupt rate control register (INTDSTn_RATE_CNTL)
  3. The counter reloads and immediately starts down-counting each time the CPU writes these registers.
  4. When the rate control counter register is written, and the counter value reaches zero, the interrupt pulse generation logic is allowed to fire a single pulse if any bits in the corresponding ICSR register bits are set.
  5. If interrupt pacing is not desired for a particular interrupt destination, the CPU must still write 00000000h into the INTDSTn_RATE_CNTL register after clearing the corresponding ICSR bits to acknowledge the physical interrupt.
8. Interrupt Handling
  1. When the CPU is interrupted, it reads the ICSR registers to determine the source of the interrupt and appropriate action to take.
  2. For example, if it is a DOORBELL interrupt, the CPU will read from an L2 address that is specified by its circular buffer read pointer that is managed by software. There may be more than one circular buffer for each core. The correct circular buffer to read from and increment
    depends on the bit set in the ICSR register. The CPU then clears the status bit.