Memory
来源:互联网 发布:java高级网络编程 编辑:程序博客网 时间:2024/05/04 10:48
Reference:
http://www.xilinx.com/itp/3_1i/data/fise/xst/chap02/xst02013.htm
www.asic-world.com
RAM:
Syntax
reg [wordsize:0] array_name [0:arraysize]
E.G. reg [7:0] my_memory [0:255];
Here [7:0] is the memory width and [0:255] is the memory depth with the following parameters:
- Width : 8 bits, little endian
- Depth : 256, address 0 corresponds to location 0 in the array.
Storing Data:
my_memory [address] = Data_in;
Reading Data:
Data_out = my_memory [address];
Initializing Memories
$readmemh("file_name",mem_array,start_addr,stop_addr);
Note : start_addr and stop_addr are optional.
module memory();reg [7:0] my_memory [0:255];initial begin $readmemh("memory.list", my_memory);endendmodule
Following is the Verilog code for a single port RAM with asynchronous read.
module raminfr (clk, we, a, di, do);
input clk;
input we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
always @(posedge clk) begin
if (we)
ram[a] = di;
end
assign do = ram[a];
endmodule
Following is the Verilog code for a single port RAM with "false" synchronous read.
module raminfr (clk, we, a, di, do);
input clk;
input we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
reg [3:0] do;
always @(posedge clk) begin
if (we)
ram[a] = di;
do = ram[a];
end
endmodule
The following descriptions, featuring an additional reset of the RAM output, are also only mappable onto Distributed RAM with an additional resetable buffer on the data output as shown in the following figure:
module raminfr (clk, we, rst, a, di, do);
input clk;
input we;
input rst;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
reg [3:0] do;
always @(posedge clk) begin
if (we)
ram[a] = di;
if (rst)
do = 4'b0;
else
do = ram[a];
end
endmodule
Following is the Verilog code for a single-port RAM with synchronous read (read through).
module raminfr (clk, we, a, di, do);
input clk;
input we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
reg [4:0] read_a;
always @(posedge clk) begin
if (we)
ram[a] = di;
read_a = a;
end
assign do = ram[read_a];
endmodule
- Memory
- Memory
- memory
- memory
- Memory
- memory
- Memory
- Memory
- Memory
- Memory
- MEMORY
- memory
- memory
- memory
- memory
- memory
- Memory
- Memory
- 国外GIS平台介绍
- JSON AJAX JQuery
- java基础知识记录--异常 (摘自张孝祥整理java面试题)
- 地理信息技术
- Win7下用CreateRemoteThread线程注入
- Memory
- VIM安装配置(语法高亮显示)
- struts2之整合sitemesh(更复杂的装饰器页面)
- gcov覆盖率测试
- 三维GIS平台介绍
- C++ - 为什么析构函数不允许抛出异常
- modprobe XXX not found 解决与Depmod命令; insmod/modprobe的区别
- JS操作JSON总结
- 泛型与反射