Intel® IA-32 Architecture Learning 1

Author: Harold Wang

http://blog.csdn.net/hero7935

Overview:

Operation Mode
Typical Computer Systems
Registers/Resources

Operation Mode:

Real Mode
Intel® 8086 processor mode with a few extension that only 20 bit address memory is ceessible(1MB) and used for Linux* Boot procedure.
Protected Mode
Everything is available!
System Management Mode
A transparent mechanism for management, Not in the scope
Virtual 8086 Mode(V86 Mode)
Allows the processor to execute 8086 software in a protected, multitasking environment
Ia32e Mode
Compatibility Mode that protected Mode applications run unchanged.
64-bit Mode that 64 bit linear address, physical memory space larger that 64GB

Basci Program Execution Registers:

System Level Registers and Data Structures in IA-32 Mode

Author: Harold Wang

http://blog.csdn.net/hero7935

Address  Translation:---->2 Stage _1 Segmentation
Logical Address[16bit Segment selector+32bit offset];
Linear Address[32bit flat address space];
 

1.Segment Selector(16 bit):
--An index to GET/LDT
 
2.Segment Descriptor(8 byte):
--Specifies Segment Basse, Limit and DPL

3.Segment Register(6)
--CS,DS,ES,SS,FS,GS(you can refer to the former graph)

There are 2 MM Models: Flat Model(used in Linux), Multi-Segment Model
 

 

Address  Translation:---->2 Stage _2 Paging

When PAE disabling…
-- Page Directory Entry(4KB Page Table)

--Page Table Entry(4KB Page)

Privilege Level Check:
Protecting Ring
 
Privilege Level~CPL DPL RPL
Privilege Check

Author: Harold Wang

http://blog.csdn.net/hero7935

If Data Segment : DPL>=CPL && DPL>=RPL
If Stack Segment :DPL=CPL=RPL

Transferring to Privileged Code:

Other privileged Instructions:

Memory Management Registers:
--Control Registers:

--GDT/LDT/IDT/TR:

IDT and IDT descriptor:
IDTR register contains IDT base address and limit

Interrupt/Exception Handling:
Interrupt/Trap gate transfers control to interrupt/exception handler like a call gate.
only differs~Interrupt gate will clear IF, trap gate will not!

Author: Harold Wang

http://blog.csdn.net/hero7935

Interrupt Enabling/Disabling:
By changing EFLAGS.IF and EFLAGS.RF, EFLAGS.TF~
Clearing IF disables servicing of maskable hardware interrupt.
Setting RF disables debug exceptions for instruction breakpoint
Clearing TF disables single step breakpoint exception

Task Management Data structure:
TSS Descriptor

TSS Gate

TSS Register

Interrupt/Exception Handling may involve Stack switches if transfer to lower privileged code:

Author: Harold Wang

http://blog.csdn.net/hero7935

Thank You for Intel® Open Source Technology Center