CS8900 base address的确定方法
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·Single-Chip IEEE 802.3 Ethernet Controller with Direct ISA-Bus Interface
·Maximum Current Consumption = 55 mA (5V Supply)
·3 V or 5 V Operation
·Industrial Temperature Range
· Comprehensive Suite of Software Drivers Available
·Efficient PacketPage Architecture Operates in I/O and Memory Space, and as DMA Slave
·Full Duplex Operation
·On-Chip RAM Buffers Transmit and ReceiveFrames
·10BASE-T Port with Analog Filters, Provides:
- Automatic Polarity Detection and Correction
·AUI Port for 10BASE2, 10BASE5 and 10BASE-F
·Programmable Transmit Features:
- Automatic Re-transmission on Collision
- Automatic Padding and CRC Generation
·Programmable Receive Features:
- Stream Transfer; for Reduced CPU Overhead
- Auto-Switch Between DMA and On-Chip Memory
- Early Interrupts for Frame Pre-Processing
- Automatic Rejection of Erroneous Packets
·EEPROM Support for Jumperless Configuration
·Boot PROM Support for Diskless Systems
·Boundary Scan and Loopback Test
·LED Drivers for Link Status and LAN Activity
·Standby and Suspend Sleep Modes
The CS8900A architecture is based on a unique, highly-efficient method of accessing internal registers and buffer memory known as PacketPage. PacketPage provides a unified way of controlling the CS8900A in Memory or
I/O space that minimizes CPU overhead and simplifies software. It provides a flexible set of performance features and configuration options, allowing designers to develop Ethernet circuits that meet their particular system requirements.
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