u-boot2008.10非nand_leagcy移植mini2440，支持yaffs，附源码 ---转！！

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这篇文章写于2008.12.28日，主要记录了我移植u-boot-2008.10的过程，并附上了移植好的patch文件。移植好的u-boot-2008.10适用友善公司的mini2440和阳初公司的yc2410。其它的开发板，可能要根据相应的电路配置做稍许修改。我的移植是使用非nand-leagcy方法的，移植好的u-boot-2008.10功能除了基本功能外，加上了yaffs1映像的写入功能，加入了从nand flash启动的功能，改善了一些操作感受，往nand写入数据时，可以显示进度。在使用上要注意的是使用nand wirte.yaffs 命令写入yaffs1映像时，文

件长度参数一定要与yaffs1映像的大小完全一致，否则有可能产生假坏块。我的开发环境是vmware，kubuntu8.04。交叉编译是用crosstool0.43编译生成的arm-linux-gcc 4.1.0，libc 2.3.2。

（本人也成功移植了linux2.6.27.9到mini2440开发板上，有需要源码的，可以和我联系。EMAIL：nanjinrat@sohu.com，映像文件在此下载http://blog.chinaunix.net/u2/75270/showart.php?id=1796658 映像的使用方法见我的另一篇文章。http://blog.chinaunix.net/u2/75270/showart.php?id=1836713）

一直想自已移植一套u-boot，但因为工作忙，一直都没有做，最近时间比较多，买了一套友善之臂的mini2440开发板，此板电路与该公司之前的QQ2440基本一至。而该开发板自带的u-boot的移植的还不很完善，于是下决心自已移植u-boot。要移植就用最新版的u-boot移植，于是决定在u-boot.2008.10版上进行移植，此版是2008年10月的新版，于之前的版本有较大改动，所以版本号也没有延续以前的编号方式，而改为2008.10。我的移植目的，是要能同时持S3C2440,S3C2410（手中还有一块阳初公司出的S3C2410开发板），从nand flash启动u-boot，因为目前大多数应用都是只有nand flash的，所以没打算从nor flash启动。支持tftp的使用，也就说要移植网卡的驱动，mini2440和阳初的s3c2410自带的linux都是使用yaffs文件系统作为根文件系统的，因此，u-boot还要能支持yaffs映像的烧写。在此我将移植过程记录下来，以方便大家在移植此版u-boot时参考。为了方便整个移植过程中的调试，我把移植过程分为0~6共7个阶段。每个阶段完成时，u-boot都是可以正常运行的，因此，你可以根据自已的要求，决定移植工作做到哪一阶段。为了同时支持S3C2440和S3C2410，我在移植时，同时加入两种代码，使用config_s3c2440，config_s3c2410这样的宏定义来决定编译哪种代码。如果你不需要同时支持两个CPU，你可以只加入一种代码。所有代码不在此列出，大家可以看我上传的移植好的u-boot。我在下面给出针对S3C2440移植的详细说明，S3C2410的移植比较简单，参考2440的移植即可，不另说明了。不同阶段的详细代码可以阅读patch文件。

第0阶段：
本阶段任务，是在u-boot系统中，建立起自已的开发板体系。我先建立mini2440板的体系。方法如下。hugerat是我的网名，你可以根据需要更改。
1 打开u-boot主目录下的makefile，找到smdk2410_config，在其下，仿照它的格式加入如下语句
rat2440_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t rat2440 hugerat s3c24x0

各项的意思如下:
arm: CPU的架构(ARCH)
arm920t: CPU的类型(CPU)，其对应于cpu/arm920t子目录。
rat2440: 开发板的型号(BOARD)，对应于board/hugerat/rat2440目录。
hugerat: 开发者/或经销商(vender)。
s3c24x0: 片上系统(SOC)。

此步是为了加入自已的开发板，非必须也可以在现有的开发板基础上修改。

2修改CROSS_COMPILE为自已的arm gcc编译器，我使用的是系统默认的arm-linux-gcc，故不必再修改相应的CROSS_COMPILE项。

3 在/board子目录中建立自己的开发板rat2440目录由于我在上一步板子的开发者/或经销商(vender)中填了 hugerat ，所以开发板rat2440目录一定要建在/board子目录中的hugerat

目录下，否则编译会出错。
然后，将smdk2410目录下的文件考入此目录中。
并将其中的smdk2410.c改名为rat2440.c

还要记得修改自己的开发板rat2440目录下的Makefile文件，不然编译时会出错：

COBJS := rat2440.o flash.o

4 在include/configs/中建立配置头文件
将smdk2410的相应头文件复制一份在相同目录下。并改名为rat2440.h

5 回到u-boot主目录，make rat2440_config，再make，编译生成u-boot.bin成功。

建立S3C410板的方法同上，仅将2440改为2410即可。不重复了。

第0阶段完成。

第1阶段
本版u-boot依然没有提供对S3C2440的支持，因此本阶段任务是加入S3C2440相关的代码，使得u-boot可以在s3c2440上正常工作。但

没有增加任何附加功能。
在下列文件中加入标注为/*by hugerat,phase 1---*/的代码。其中，被注释掉的代码为原代码。
/cpu/arm920t/start.s (加入S3C2440的时钟相关的寄存器定义，加入时钟初始化代码，以使S3C2440工作在405MHz)
board/hugerat/rat2440/lowlevel_init.s(加入S3C2440内存控制寄存器的定义)
board/hugerat/rat2440/rat2440.c (修改GPIO，PLL的设置，应注意GPBCON的设置，不要让蜂鸣器响)
include/configs/rat2440.h(设定环境变量)
以下文件主要加入CONFIG_S3C2440宏定义以使得编译一些S3C2410的代码，和加入led灯的控制。以指示u-boot程序进程。
/inlcude/s3c24x0.h
cpu/arm920t/s3c24x0/interrupts.c(这里还要加入CONFIG_rat2440和CONFIG_rat2410)
/cpu/arm920t/s3c24x0/serial.c
cpu/arm920t/s3c24x0/speed.c
cpu/arm920t/s3c24x0/usb_ohci.c
/cpu/arm920t/s3c24x0/usb.c cpu/arm920t/s3c24x0/i2c.c
drivers/usb/usb_ohci.c
drivers/rtc/s3c24x0_rtc.c
/lib_arm/board.c

编译成功。将u-boot.bin烧入nor-flash即可运行。
但是为方便使用，同时，也是方便u-boot的调试。因此，我要将此u-boot代码再做一修改，使其可以在内存中运行。这样，可以用

开发板自带的vivi将其下载到内存中，再在内存中运行u-boot。要想它在内存中运行，方法很简单，将/root/u-boot-

1.3.1/cpu/arm920t中的start.s中

#ifndef CONFIG_SKIP_LOWLEVEL_INIT

bl cpu_init_crit

#endif

此段代码中的bl cpu_init_crit注释掉，即不进行CPU的初始化工作（此工作，当前在板子上运行的vivi已完成，故不能再次进行）

，即改为

#ifndef CONFIG_SKIP_LOWLEVEL_INIT

@bl cpu_init_crit

#endif

修改/board/hugerat/rat2440/config.mk中text_base 值为0x33000000

使用vivi命令load ram 0x33000000 0x17ea8 x将u-boot.bin装入内存。再用go 0x33000000命令，即可。

至此，第1阶段工作完成。

第2阶段
本阶段任务，是给u-boot移植dm9000的网卡驱动。
u-boot自带网卡驱动，所以只要做些设置即可。
在下列文件中加入标志为/*by hugerat,phase 2----*/的代码.
/include/configs/rat2440.h （加入dm9000定义，加入ping命令定义）
此时，编译通过，但ping时，报`ethaddr' not set错误。
研究原代码，发现#define CONFIG_ETHADDR 08:00:3e:26:0a:5b被注释掉，恢复，并改变原来默认的IP地址。重新编译后，可以

ping通网络了。（也可以在u-boot启动后，修改相关参数，但因为现阶段还没有支持nandflash，参数无法保存，故在此改变较为方

便）
又发现，ping是能ping通了，但报could not establish link(不能建立链接)的错。不影响使用。参考网上的资料，发现这是因为

在网卡驱动中，/home/lijin/u-boot-rat/drivers/net/dm9000.c,有一段程序试图连接网卡的MII接口，而实际上MII接口并未使用

，所以有十秒的等待时间，且报错，将此段程序注释掉即可。
到此，本阶段任务完成。

第3阶段
本阶段任务，移植nand-flash驱动，注意此阶段工作仅是让u-boot可以操作读写nand flash。还不能让它从nand flash启动。

首先,要说明一下CFG_NAND_LEGACY的使用。在u-boot的/drivers/mtd/下有两个目录，分别是nand和nand_legacy。在nand目录下的

是nand的初始化函数和nand的操作读写函数，是使用linux的mtd构架的。此目录下的文件，只有在定义了CFG_CMD_NAND宏和没有定

义CFG_NAND_LEGACY宏的情况下才会被编译。在nand_leagcy目录下的文件也是是实现nand相关操作命令，如read,write等命令的功

能，但不是使用linux的mtd构架。此目录下的文件，只有在定义了CFG_CMD_NAND和定义了CFG_NAND_LEGACY宏的情况下才会定义。此

目录下的文件u-boot组织已不推荐使用。事实上，此版中，S3C2410构架已不支持对nand_leagcy，因此，我在移植中，是用的不定

义CFG_NAND_LEGACY的方式，即非nand_leagcy方式。

在/include/configs/rat2440.h中加标注为by hugerat,phase3的代码段，这段代码是让u-boot启用其自带nand flash驱动，并设置

相应的nand flash参数。
此时，试编译一下，通过。要说明的是，此版的u-boot已自带board_nand_init()，此函数在/cpu/arm920t/s3c24x0/nand.c中实现

。并且此版已不支持定义CFG_NAND_LEGACY，如定义此宏，则编译是会报 #error "U-Boot legacy NAND support not available

for S3C2410"的错误。故此版已不能使用网上流传非nand_leagcy方式的自加nand flash初始化函数的方法，只能用其自带的初始化

函数
下载到内存中运行，报None nand devices!!!，这是当然的。因为S3C2410和S3C2440在FLASH控制器上，差别较大，必须改写代码。

改写主要在/cpu/arm920t/s3c24x0/nand.c中进行。（此文件内是与芯片紧密相关的代码），一是board_nand_init函数，一是

s3c2410_hwcontrol，参照2440的手册，改写相关代码。还要在此文件的开始部分加入S3C2440 nand flash控制器相关寄存器的定义

。改写的代码标注同上。改写完毕后，u-boot可以识别出nand flash芯片是64MB的，但还不能识别是什么芯片。

在/driver/mtd/nand/nand_base.c中的nand_get_flash_type函数结尾，修改MTDDEBUG语句，改为printf，再编译，可以正常显示芯

片了。但nand write功能不正常，即没报错，实际上也没有写进去。

探讨原因后发现，原来是u-boot自带的nand-flash驱动（不定义nand_leagcy），是基于mtd驱动的。在默认情况下，不进行写入正

确与否的校验。要定义CONFIG_MTD_NAND_VERIFY_WRITE宏才能进行写入校验。关于ECC校验，mtd驱动默认是用sotf_ecc的。加入宏

定义后，u-boot报write error了。
在此我卡了很久，最后才发现是u-boot.2008.10自带的S3C2410的s3c2410_hwcontrol函数有错。在此函数中，把chip->IO_ADDR_W值

改写了，导致在写数据时出现错误。将此错误修正后，nand write正常了。修正方法是使用一全局变量替代chip->IO_ADDR_W。

接下来，在rat2440.h中加入#define CONFIG_ENV_IS_IN_NAND 1注掉原来的#define CONFIG_ENV_IS_IN_FLASH 1，加入

#define CONFIG_ENV_OFFSET 0x30000 注掉原来的#define CFG_ENV_OFFSET 0x30000。编译。saveenv功能也正常了。
至此，nand-flash驱动移植完成。

测试，nand write 0x30000000 0x40000 0x40000时，成功。用nand read也成功读出。此处要说明的，如果用vivi烧写信息到nand

中，再用u-boot读取，会报错，应该是ECC校验不是由同一软件产生所至。
此阶段完成。

第4阶段
本阶段任务是将u-boot改写为从nand-flash启动。
首先，将/cpu/arm920t/start.s中第一阶段中为了从内存中启动而屏蔽掉的语句恢复。加入标注为/*by hugerat,phase 4----*/的

语句，为了兼容S3C2410，同时也加入S3C2410 nand boot 相关代码。同时，在/board/hugerat/rat2440/lower_init.s中，根据开

发板电路，对内存相关的几个寄存器定义进行调整。整个启动代码参考了vivi的代码。因此，将vivi的nand_read.c（支持S3C2440

的vivi，此文件中的读nand函数是直接操作nand flash的，与u-boot自带，适合用于启动时用。）考入/board/hugerat/rat2440目

录下。并修改目录下的makefile，使nand_read.c被编译。
编译，成功，将u-boot烧入nand flash，能成功从nand启动了。

第5阶段
本阶段任务是实现u-boot通过nfs引导友善提供的linux2.6.13的内核。
友善的linux并没有提供make uImage命令，需要添加。将u-boot的tools目录下的mkimage拷到开发机linux系统下的/usr/bin目录下

。在linux的/arch/arm/makefile中和/arch/arm/boot/makefile中，可以找到zImage的项目，仿照它添加uImage项目。

这个问题解决后，就是要用u-boot引导linux内核了，我用的是扬创提供的linux2.6.13的内核，扬创提供的内核，loadaddress和

entry都是30008000，我用u-boot1.2中的bootcmd参数，u-boot1.3.1 bootm却不能引导，报bad magic number，看了bootm的相关资

料，得知，如果我们没用mkimage对内核进行处理的话，那直接把内核下载到0x30008000再运行就行，内核会自解压运行（不过内核

运行需要一个tag来传递参数，而这个tag建议是由bootloader提供的，在u-boot下默认是由bootm命令建立的）。

2）如果使用mkimage生成内核镜像文件的话，会在内核的前头加上了64byte的信息，供建立tag之用。bootm命令会首先判断bootm

xxxx 这个指定的地址xxxx是否与-a指定的加载地址相同。
(1)如果不同的话会从这个地址开始提取出这个64byte的头部，对其进行分析，然后把去掉头部的内核复制到-a指定的load地址中去

运行之
(2)如果相同的话那就让其原封不同的放在那，但-e指定的入口地址会推后64byte，以跳过这64byte的头部。

Bootm在没有参数时，是采用rat2440.h中的#define CFG_LOAD_ADDR 的地址的，而我用bootm就是没有使用参数，所以出错了。正确

的做法应该是用nand read命令将内核从nand flash中读到内存的某一地址中（注意不要与其它已分配的内存冲突），然后再用

bootm 加地址参数，即可引导，也可以在上述的文件中，将CFG_LOAD_ADDR的地址定义为此地址，再用bootm就可以了.
我设定bootcmd环境变量为tftp 0x31000000 uImage; bootm 0x31000000,注意地址不能为0x30008000,否则报错.

做完这此，内核可以引导了，但却停在starting kernel不动了，好在我以前做过vivi+linux2.6.22的移植，知道此问题多半是由于

mach_type不同而造成的。在u-boot中，此mach_type是由rat2440.c中的这段代码定义的

#if defined(CONFIG_S3C2440)

/* arch number of S3C2440 -Board */

//gd->bd->bi_arch_number = 5244 ; //改为和内核的MACH＿TYPE一至

gd->bd->bi_arch_number = MACH_TYPE_MINI2440 ;

#endif

你可以直接在这里改数字，也可以在include/asm-arm/mach_types.h的文件中，改MACH_TYPE_S3C2440的数值。将数值改为和内核的

mach_type一至。至于内核的mach_type可以在内核linux源代码下的arch/arm/tools中的mach_types文件查看到。

此时，又发现内核不能通过nfs引导。查资料后得知是因为u-boot没有传递参数给内核。原来是rat2440.h中少定义了几个宏。补上

。
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */

#define CONFIG_SETUP_MEMORY_TAGS 1

#define CONFIG_INITRD_TAG 1

至此，u-boot已能正常引导linux启动了。第5阶段完成。

第6阶段
本阶段任务，是给u-boot加入烧写yaffs映像文件的功能。
网上有很多文章已经有介绍如何加入此功能，方法也不复杂。但我移植的u-boot.2008.10版，在nand flash的操作上与之前的版本

有了很大的区别。这些文章介绍的方法已不能在此版中应用。于是我只好自已根据u-boot的源代码，yaffs映像文件的格式，自已编

修改了u-boot.2008.10的代码，让它可以实现yaffs的烧写，因为我用的开发板的nand flash是k9f1208，只能使用yaffs1，所以我

的修改代码暂时只能支持yaffs1格式的映像。（要支持yaffs2也不难，但因为无法验证，所以就没有做尝试。）
修改方法如下：
在/common/com_nand.c中do_nand函数中，加入三段/*by hugerat,phase6---*/标注的代码，实现对nand write.yaffs命令的支持。

此代码中，要用到mtd_info结构中的两个变量，这两个变量本来是没有的，所以要在include/linux/mtd/mtd.h的mtd_info结构体定

义中加入。
在/drivers/mtd/nand/nand_util.c的nand_write_skip_bad函数中，两段程序，一段是为了计算正常数据的长度，一段是为了在写

入一段数据后，数据指针能正常跳到下一段数据。
在/drivers/mtd/nand/nand_base.c的nand_write函数中，加入一段把正常数据与oob数据分离的代码，再加入页写时的模式设置为

MTD_OOB_RAW，使页写时，不进行ECC的校验和加入。（ECC的校验在yaffs的oob数据中已自带了，不能重写。）此模式下，写入正常

数据后，会把oob数据缓存的数据写入nand的oob区。
至此，u-boot.2008.10的移植工作全部完成。

最后说明一下，关于阳初2410的移植，因为上面的代码中已加入S3C2410相关代码，移植时，只需参考S3C2440，新建一个开发板体

系，新建时，将rat2440目录下的文件拷贝到rat2410下，将重命名S3C2440.c为S3C2410.c，修改makefile,加上s3c2410.o 去掉

s3c2440.o，拷贝rat2440.h为rat2410.h，将其中的CONFIG_S3C2440注掉，加上CONFIG_S3C2410。在u-boot总目录下的makefile中

rat2440_config下添加
rat2410_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t rat2410 hugerat s3c24x0
因为阳初的板用的是cs8900，因此要在rat2410.h中注掉DM9000的定义，添加CS8900的。
再make rat2410_config，再make，即可。

文章最后，为方便网友，我把patch文件附上。patch文件使用方法是在linux下建立u-boot-rat.patch文件，将patch文件的内容拷

入u-boot-rat.patch文件中。下载u-boot-2008.10.tar.bz2，在这里下载ftp://ftp.denx.de/pub/u-boot/，用tar -xvf u-bot-

2008.19.tar.bz2解压到u-boot-2008.10目录，把u-boot-rat.patch文件拷贝到此目录所在同级目录下。执行patch -p0 < u-boot-

rat.patch。完成后，进u-boot-2008.10目录，执行make rat2440_config，再make即可生成u-boot.bin，如是2410，则执行make

rat2410_config即可，我在mini2440,阳初的2410上试过，功能正常。其它开发板的也可一试。

附patch文件:

可能发贴字数有限制，下面的补丁文件不全。可以在此下载全部补丁。

文件: u-boot-rat.rar 大小: 20KB 下载: 下载

diff -Nurp u-boot-2008.10/board/hugerat/rat2410/config.mk u-boot-rat/board/hugerat/rat2410/config.mk
--- u-boot-2008.10/board/hugerat/rat2410/config.mk 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-rat/board/hugerat/rat2410/config.mk 2008-12-15 23:03:59.000000000 +0800
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+#
+
+#
+# SMDK2410 has 1 bank of 64 MB DRAM
+#
+# 3000'0000 to 3400'0000
+#
+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
+# optionally with a ramdisk at 3080'0000
+#
+# we load ourself to 33F8'0000
+#
+# download area is 3300'0000
+#
+
+
+TEXT_BASE = 0x33f80000
diff -Nurp u-boot-2008.10/board/hugerat/rat2410/flash.c u-boot-rat/board/hugerat/rat2410/flash.c
--- u-boot-2008.10/board/hugerat/rat2410/flash.c 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-rat/board/hugerat/rat2410/flash.c 2008-10-19 03:30:31.000000000 +0800
@@ -0,0 +1,433 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush (void);
+
+
+#define FLASH_BANK_SIZE PHYS_FLASH_SIZE
+#define MAIN_SECT_SIZE 0x10000 /* 64 KB */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY  0x000000F0
+#define CMD_UNLOCK1  0x000000AA
+#define CMD_UNLOCK2  0x00000055
+#define CMD_ERASE_SETUP  0x00000080
+#define CMD_ERASE_CONFIRM 0x00000030
+#define CMD_PROGRAM  0x000000A0
+#define CMD_UNLOCK_BYPASS 0x00000020
+
+#define MEM_FLASH_ADDR1  (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
+#define MEM_FLASH_ADDR2  (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
+
+#define BIT_ERASE_DONE  0x00000080
+#define BIT_RDY_MASK  0x00000080
+#define BIT_PROGRAM_ERROR 0x00000020
+#define BIT_TIMEOUT  0x80000000 /* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+ int i, j;
+ ulong size = 0;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+  ulong flashbase = 0;
+
+  flash_info[i].flash_id =
+#if defined(CONFIG_AMD_LV400)
+   (AMD_MANUFACT & FLASH_VENDMASK) |
+   (AMD_ID_LV400B & FLASH_TYPEMASK);
+#elif defined(CONFIG_AMD_LV800)
+   (AMD_MANUFACT & FLASH_VENDMASK) |
+   (AMD_ID_LV800B & FLASH_TYPEMASK);
+#else
+#error "Unknown flash configured"
+#endif
+   flash_info[i].size = FLASH_BANK_SIZE;
+  flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+  memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+  if (i == 0)
+   flashbase = PHYS_FLASH_1;
+  else
+   panic ("configured too many flash banks!/n");
+  for (j = 0; j < flash_info[i].sector_count; j++) {
+   if (j <= 3) {
+    /* 1st one is 16 KB */
+    if (j == 0) {
+     flash_info[i].start[j] =
+      flashbase + 0;
+    }
+
+    /* 2nd and 3rd are both 8 KB */
+    if ((j == 1) || (j == 2)) {
+     flash_info[i].start[j] =
+      flashbase + 0x4000 + (j -
+              1) *
+      0x2000;
+    }
+
+    /* 4th 32 KB */
+    if (j == 3) {
+     flash_info[i].start[j] =
+      flashbase + 0x8000;
+    }
+   } else {
+    flash_info[i].start[j] =
+     flashbase + (j - 3) * MAIN_SECT_SIZE;
+   }
+  }
+  size += flash_info[i].size;
+ }
+
+ flash_protect (FLAG_PROTECT_SET,
+         CFG_FLASH_BASE,
+         CFG_FLASH_BASE + monitor_flash_len - 1,
+         &flash_info[0]);
+
+ flash_protect (FLAG_PROTECT_SET,
+         CONFIG_ENV_ADDR,
+         CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case (AMD_MANUFACT & FLASH_VENDMASK):
+  printf ("AMD: ");
+  break;
+ default:
+  printf ("Unknown Vendor ");
+  break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case (AMD_ID_LV400B & FLASH_TYPEMASK):
+  printf ("1x Amd29LV400BB (4Mbit)/n");
+  break;
+ case (AMD_ID_LV800B & FLASH_TYPEMASK):
+  printf ("1x Amd29LV800BB (8Mbit)/n");
+  break;
+ default:
+  printf ("Unknown Chip Type/n");
+  goto Done;
+  break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors/n",
+  info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++) {
+  if ((i % 5) == 0) {
+   printf ("/n   ");
+  }
+  printf (" %08lX%s", info->start[i],
+   info->protect[i] ? " (RO)" : "     ");
+ }
+ printf ("/n");
+
+      Done:;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ ushort result;
+ int iflag, cflag, prot, sect;
+ int rc = ERR_OK;
+ int chip;
+
+ /* first look for protection bits */
+
+ if (info->flash_id == FLASH_UNKNOWN)
+  return ERR_UNKNOWN_FLASH_TYPE;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+  return ERR_INVAL;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) !=
+     (AMD_MANUFACT & FLASH_VENDMASK)) {
+  return ERR_UNKNOWN_FLASH_VENDOR;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+  if (info->protect[sect]) {
+   prot++;
+  }
+ }
+ if (prot)
+  return ERR_PROTECTED;
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ cflag = icache_status ();
+ icache_disable ();
+ iflag = disable_interrupts ();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+  printf ("Erasing sector %2d ... ", sect);
+
+  /* arm simple, non interrupt dependent timer */
+  reset_timer_masked ();
+
+  if (info->protect[sect] == 0) { /* not protected */
+   vu_short *addr = (vu_short *) (info->start[sect]);
+
+   MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+   MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+   MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+   MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+   MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+   *addr = CMD_ERASE_CONFIRM;
+
+   /* wait until flash is ready */
+   chip = 0;
+
+   do {
+    result = *addr;
+
+    /* check timeout */
+    if (get_timer_masked () >
+        CFG_FLASH_ERASE_TOUT) {
+     MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+     chip = TMO;
+     break;
+    }
+
+    if (!chip
+        && (result & 0xFFFF) & BIT_ERASE_DONE)
+     chip = READY;
+
+    if (!chip
+        && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
+     chip = ERR;
+
+   } while (!chip);
+
+   MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+   if (chip == ERR) {
+    rc = ERR_PROG_ERROR;
+    goto outahere;
+   }
+   if (chip == TMO) {
+    rc = ERR_TIMOUT;
+    goto outahere;
+   }
+
+   printf ("ok./n");
+  } else { /* it was protected */
+
+   printf ("protected!/n");
+  }
+ }
+
+ if (ctrlc ())
+  printf ("User Interrupt!/n");
+
+      outahere:
+ /* allow flash to settle - wait 10 ms */
+ udelay_masked (10000);
+
+ if (iflag)
+  enable_interrupts ();
+
+ if (cflag)
+  icache_enable ();
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_hword (flash_info_t * info, ulong dest, ushort data)
+{
+ vu_short *addr = (vu_short *) dest;
+ ushort result;
+ int rc = ERR_OK;
+ int cflag, iflag;
+ int chip;
+
+ /*
+ * Check if Flash is (sufficiently) erased
+ */
+ result = *addr;
+ if ((result & data) != data)
+  return ERR_NOT_ERASED;
+
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ cflag = icache_status ();
+ icache_disable ();
+ iflag = disable_interrupts ();
+
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+ MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
+ *addr = CMD_PROGRAM;
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ /* wait until flash is ready */
+ chip = 0;
+ do {
+  result = *addr;
+
+  /* check timeout */
+  if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+   chip = ERR | TMO;
+   break;
+  }
+  if (!chip && ((result & 0x80) == (data & 0x80)))
+   chip = READY;
+
+  if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
+   result = *addr;
+
+   if ((result & 0x80) == (data & 0x80))
+    chip = READY;
+   else
+    chip = ERR;
+  }
+
+ } while (!chip);
+
+ *addr = CMD_READ_ARRAY;
+
+ if (chip == ERR || *addr != data)
+  rc = ERR_PROG_ERROR;
+
+ if (iflag)
+  enable_interrupts ();
+
+ if (cflag)
+  icache_enable ();
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ int l;
+ int i, rc;
+ ushort data;
+
+ wp = (addr & ~1); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+  data = 0;
+  for (i = 0, cp = wp; i < l; ++i, ++cp) {
+   data = (data >> 8) | (*(uchar *) cp << 8);
+  }
+  for (; i < 2 && cnt > 0; ++i) {
+   data = (data >> 8) | (*src++ << 8);
+   --cnt;
+   ++cp;
+  }
+  for (; cnt == 0 && i < 2; ++i, ++cp) {
+   data = (data >> 8) | (*(uchar *) cp << 8);
+  }
+
+  if ((rc = write_hword (info, wp, data)) != 0) {
+   return (rc);
+  }
+  wp += 2;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 2) {
+  data = *((vu_short *) src);
+  if ((rc = write_hword (info, wp, data)) != 0) {
+   return (rc);
+  }
+  src += 2;
+  wp += 2;
+  cnt -= 2;
+ }
+
+ if (cnt == 0) {
+  return ERR_OK;
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+  data = (data >> 8) | (*src++ << 8);
+  --cnt;
+ }
+ for (; i < 2; ++i, ++cp) {
+  data = (data >> 8) | (*(uchar *) cp << 8);
+ }
+
+ return write_hword (info, wp, data);
+}
diff -Nurp u-boot-2008.10/board/hugerat/rat2410/lowlevel_init.S u-boot-rat/board/hugerat/rat2410/lowlevel_init.S
--- u-boot-2008.10/board/hugerat/rat2410/lowlevel_init.S 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-rat/board/hugerat/rat2410/lowlevel_init.S 2008-12-10 19:08:15.000000000 +0800
@@ -0,0 +1,191 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+/*
+ *
+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
+ *
+ * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
+ *
+ */
+
+#define BWSCON 0x48000000
+
+/* BWSCON */
+#define DW8   (0x0)
+#define DW16   (0x1)
+#define DW32   (0x2)
+#define WAIT   (0x1<<2)
+#define UBLB   (0x1<<3)
+
+#define B1_BWSCON  (DW32)
+#define B2_BWSCON  (DW16)
+#define B3_BWSCON  (DW16 + WAIT + UBLB)
+/*by hugerat,phase 4-----------*/
+//#define B4_BWSCON  (DW16)
+#define B4_BWSCON  (DW16 + WAIT + UBLB)
+/*-----------------------------*/
+#define B5_BWSCON  (DW16)
+#define B6_BWSCON  (DW32)
+#define B7_BWSCON  (DW32)
+
+/* BANK0CON */
+#define B0_Tacs   0x0 /* 0clk */
+#define B0_Tcos   0x0 /* 0clk */
+#define B0_Tacc   0x7 /* 14clk */
+#define B0_Tcoh   0x0 /* 0clk */
+#define B0_Tah   0x0 /* 0clk */
+#define B0_Tacp   0x0
+#define B0_PMC   0x0 /* normal */
+
+/* BANK1CON */
+#define B1_Tacs   0x0 /* 0clk */
+#define B1_Tcos   0x0 /* 0clk */
+#define B1_Tacc   0x7 /* 14clk */
+#define B1_Tcoh   0x0 /* 0clk */
+#define B1_Tah   0x0 /* 0clk */
+#define B1_Tacp   0x0
+#define B1_PMC   0x0
+
+#define B2_Tacs   0x0
+#define B2_Tcos   0x0
+#define B2_Tacc   0x7
+#define B2_Tcoh   0x0
+#define B2_Tah   0x0
+#define B2_Tacp   0x0
+#define B2_PMC   0x0
+
+#define B3_Tacs   0x0 /* 0clk */
+#define B3_Tcos   0x3 /* 4clk */
+#define B3_Tacc   0x7 /* 14clk */
+#define B3_Tcoh   0x1 /* 1clk */
+#define B3_Tah   0x0 /* 0clk */
+#define B3_Tacp   0x3     /* 6clk */
+#define B3_PMC   0x0 /* normal */
+
+/*by hugerat,phase 4----------------*/
+//#define B4_Tacs   0x0 /* 0clk */
+//#define B4_Tcos   0x0 /* 0clk */
+//#define B4_Tacc   0x7 /* 14clk */
+//#define B4_Tcoh   0x0 /* 0clk */
+//#define B4_Tah   0x0 /* 0clk */
+//#define B4_Tacp   0x0
+//#define B4_PMC   0x0 /* normal */
+
+#define B4_Tacs   0x0 /* 0clk */
+#define B4_Tcos   0x3 /* 4clk */
+#define B4_Tacc   0x7 /* 14clk */
+#define B4_Tcoh   0x1 /* 1clk */
+#define B4_Tah   0x3 /* 4clk */
+#define B4_Tacp   0x6 /* 6clk */
+#define B4_PMC   0x0 /* normal */
+/*----------------------------------*/
+#define B5_Tacs   0x0 /* 0clk */
+#define B5_Tcos   0x0 /* 0clk */
+#define B5_Tacc   0x7 /* 14clk */
+#define B5_Tcoh   0x0 /* 0clk */
+#define B5_Tah   0x0 /* 0clk */
+#define B5_Tacp   0x0
+#define B5_PMC   0x0 /* normal */
+
+#define B6_MT   0x3 /* SDRAM */
+#define B6_Trcd   0x1
+#define B6_SCAN   0x1 /* 9bit */
+
+#define B7_MT   0x3 /* SDRAM */
+#define B7_Trcd   0x1 /* 3clk */
+#define B7_SCAN   0x1 /* 9bit */
+
+/*by hugerat ,phase 1-------------------------*/
+/* REFRESH parameter */
+#define REFEN   0x1 /* Refresh enable */
+#define TREFMD   0x0 /* CBR(CAS before RAS)/Auto refresh */
+//#define Trp   0x0 /* 2clk */
+#define Trc   0x3 /* 7clk */
+#define Tchr   0x2 /* 3clk */
+//#define REFCNT   1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+/**************************************/
+
+
+# if defined(CONFIG_S3C2440)
+#define Trp            0x2    /* 4clk */
+#define REFCNT            1012
+#else
+#define Trp            0x0    /* 2clk */
+#define REFCNT            0x0459
+#endif
+/*-------------------------------------*/
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+ /* memory control configuration */
+ /* make r0 relative the current location so that it */
+ /* reads SMRDATA out of FLASH rather than memory ! */
+
+ ldr     r0, =SMRDATA
+ ldr r1, _TEXT_BASE
+ sub r0, r0, r1
+ ldr r1, =BWSCON /* Bus Width Status Controller */
+ add     r2, r0, #13*4
+0:
+ ldr     r3, [r0], #4
+ str     r3, [r1], #4
+ cmp     r2, r0
+ bne     0b
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+/* the literal pools origin */
+
+SMRDATA:
+    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+

(B7_BWSCON<<28))
+    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32
+    .word 0x30
+    .word 0x30
diff -Nurp u-boot-2008.10/board/hugerat/rat2410/Makefile u-boot-rat/board/hugerat/rat2410/Makefile
--- u-boot-2008.10/board/hugerat/rat2410/Makefile 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-rat/board/hugerat/rat2410/Makefile 2008-12-16 10:33:56.000000000 +0800
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := rat2410.o nand_read.o flash.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff -Nurp u-boot-2008.10/board/hugerat/rat2410/nand_read.c u-boot-rat/board/hugerat/rat2410/nand_read.c
--- u-boot-2008.10/board/hugerat/rat2410/nand_read.c 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-rat/board/hugerat/rat2410/nand_read.c 2008-12-16 11:14:08.000000000 +0800
@@ -0,0 +1,114 @@
+#include <config.h>
+
+#define __REGb(x) (*(volatile unsigned char *)(x))
+#define __REGi(x) (*(volatile unsigned int *)(x))
+#define NF_BASE 0x4e000000
+
+
+#if defined(CONFIG_S3C2440)
+
+#define NFCONF __REGi(NF_BASE + 0x0)
+#define NFCONT __REGi(NF_BASE + 0x4)
+#define NFCMD __REGb(NF_BASE + 0x8)
+#define NFADDR __REGb(NF_BASE + 0xC)
+#define NFDATA __REGb(NF_BASE + 0x10)
+#define NFSTAT __REGb(NF_BASE + 0x20)
+
+//#define GPDAT       __REGi(GPIO_CTL_BASE+oGPIO_F+oGPIO_DAT)
+
+#define NAND_CHIP_ENABLE (NFCONT &= ~(1<<1))
+#define NAND_CHIP_DISABLE (NFCONT |= (1<<1))
+#define NAND_CLEAR_RB (NFSTAT |= (1<<2))
+#define NAND_DETECT_RB { while(! (NFSTAT&(1<<2)));}
+
+#define BUSY 4
+inline void wait_idle(void) {
+ while(!(NFSTAT & BUSY));
+ NFSTAT |= BUSY;
+}
+
+#define NAND_SECTOR_SIZE 512
+#define NAND_BLOCK_MASK (NAND_SECTOR_SIZE - 1)
+
+/* low level nand read function */
+int
+nand_read_ll(unsigned char *buf, unsigned long start_addr, int size)
+{
+ int i, j;
+
+ if ((start_addr & NAND_BLOCK_MASK) || (size & NAND_BLOCK_MASK)) {
+ return -1; /* invalid alignment */
+ }
+
+ NAND_CHIP_ENABLE;
+
+ for(i=start_addr; i < (start_addr + size);) {
+ /* READ0 */
+  NAND_CLEAR_RB;
+  NFCMD = 0;
+
+  /* Write Address */
+  NFADDR = i & 0xff;
+  NFADDR = (i >> 9) & 0xff;
+  NFADDR = (i >> 17) & 0xff;
+  NFADDR = (i >> 25) & 0xff;
+
+  NAND_DETECT_RB;
+
+  for(j=0; j < NAND_SECTOR_SIZE; j++, i++) {
+  *buf = (NFDATA & 0xff);
+  buf++;
+  }
+ }
+ NAND_CHIP_DISABLE;
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_S3C2410)
+
+#define NFCONF __REGi(NF_BASE + 0x0)
+#define NFCMD __REGb(NF_BASE + 0x4)
+#define NFADDR __REGb(NF_BASE + 0x8)
+#define NFDATA __REGb(NF_BASE + 0xc)
+#define NFSTAT __REGb(NF_BASE + 0x10)
+#define BUSY 1
+
+#define NAND_SECTOR_SIZE 512
+#define NAND_BLOCK_MASK (NAND_SECTOR_SIZE - 1)
+
+inline void wait_idle(void) {
+ int i;
+ while(!(NFSTAT & BUSY))
+ for(i=0; i<10; i++);
+}
+/* low level nand read function */
+int
+nand_read_ll(unsigned char *buf, unsigned long start_addr, int size)
+{
+ int i, j;
+ if ((start_addr & NAND_BLOCK_MASK) || (size & NAND_BLOCK_MASK)) {
+ return -1; /* invalid alignment */
+ }
+ /* chip Enable */
+ NFCONF &= ~0x800;
+ for(i=0; i<10; i++);
+ for(i=start_addr; i < (start_addr + size);) {
+ /* READ0 */
+ NFCMD = 0;
+ /* Write Address */
+ NFADDR = i & 0xff;
+ NFADDR = (i >> 9) & 0xff;
+ NFADDR = (i >> 17) & 0xff;
+ NFADDR = (i >> 25) & 0xff;
+ wait_idle();
+ for(j=0; j < NAND_SECTOR_SIZE; j++, i++) {
+ *buf = (NFDATA & 0xff);
+ buf++;
+ }
+ }
+ /* chip Disable */
+ NFCONF |= 0x800; /* chip disable */
+ return 0;
+}
+#endif
diff -Nurp u-boot-2008.10/board/hugerat/rat2410/rat2410.c u-boot-rat/board/hugerat/rat2410/rat2410.c
--- u-boot-2008.10/board/hugerat/rat2410/rat2410.c 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-rat/board/hugerat/rat2410/rat2410.c 2008-12-16 11:56:17.000000000 +0800
@@ -0,0 +1,178 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <s3c2410.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FCLK_SPEED 1
+
+#if FCLK_SPEED==0  /* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV 0xC3
+#define M_PDIV 0x4
+#define M_SDIV 0x1
+#elif FCLK_SPEED==1  /* Fout = 202.8MHz */
+/*by hugerat ,phase 1-------------*/
+#if defined(CONFIG_S3C2410)
+/* Fout = 202.8MHz */
+#define M_MDIV    0xA1
+#define M_PDIV    0x3
+#define M_SDIV    0x1
+#endif
+
+#if defined(CONFIG_S3C2440)
+/* Fout = 405MHz */
+#define M_MDIV 0x7f
+#define M_PDIV 0x2
+#define M_SDIV 0x1
+#endif
+
+/*#define M_MDIV 0xA1
+#define M_PDIV 0x3
+#define M_SDIV 0x1*/
+/*------------------------*/
+#endif
+
+#define USB_CLOCK 1
+
+#if USB_CLOCK==0
+#define U_M_MDIV 0xA1
+#define U_M_PDIV 0x3
+#define U_M_SDIV 0x1
+#elif USB_CLOCK==1
+/*by hugerat ,phase 1-----*/
+#if defined(CONFIG_S3C2410)
+#define U_M_MDIV    0x48
+#define U_M_PDIV    0x3
+#endif
+
+#if defined(CONFIG_S3C2440)
+#define U_M_MDIV 0x38
+#define U_M_PDIV 0x2
+#endif
+
+/*#define U_M_MDIV 0x48
+#define U_M_PDIV 0x3*/
+
+/*------------------------*/
+#define U_M_SDIV 0x2
+#endif
+
+static inline void delay (unsigned long loops)
+{
+ __asm__ volatile ("1:/n"
+   "subs %0, %1, #1/n"
+   "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+ /* to reduce PLL lock time, adjust the LOCKTIME register */
+ clk_power->LOCKTIME = 0xFFFFFF;
+
+ /* configure MPLL */
+ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ delay (4000);
+
+ /* configure UPLL */
+ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ delay (8000);
+
+ /* set up the I/O ports */
+ gpio->GPACON = 0x007FFFFF;
+/*by hugerat ,phase 1---------------*/
+#if defined(CONFIG_rat2440_LED)
+ gpio->GPBCON = 0x00055555;
+#else
+ gpio->GPBCON = 0x00044555;
+#endif
+
+ /*gpio->GPBCON = 0x00044555;*/
+/*-----------------------------------*/
+ gpio->GPBUP = 0x000007FF;
+ gpio->GPCCON = 0xAAAAAAAA;
+ gpio->GPCUP = 0x0000FFFF;
+ gpio->GPDCON = 0xAAAAAAAA;
+ gpio->GPDUP = 0x0000FFFF;
+ gpio->GPECON = 0xAAAAAAAA;
+ gpio->GPEUP = 0x0000FFFF;
+ gpio->GPFCON = 0x000055AA;
+ gpio->GPFUP = 0x000000FF;
+ gpio->GPGCON = 0xFF95FFBA;
+ gpio->GPGUP = 0x0000FFFF;
+ gpio->GPHCON = 0x002AFAAA;
+ gpio->GPHUP = 0x000007FF;
+/*by hugerat ,phase 1-----------------------------------*/
+#if defined(CONFIG_S3C2410)
+    /* arch number of SMDK2410-Board */
+    gd->bd->bi_arch_number = MACH_TYPE_yangchu2410;
+
+#endif
+
+#if defined(CONFIG_S3C2440)
+    /* arch number of S3C2440 -Board */
+    gd->bd->bi_arch_number = MACH_TYPE_mini2440 ;
+#endif
+
+ /* arch number of SMDK2410-Board */
+ //gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
+/*------------------------------------------------------*/
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x30000100;
+
+ icache_enable();
+ dcache_enable();
+/*by hugerat ,phase 1--------------------------------*/
+# if defined(CONFIG_rat2440_LED)
+    gpio->GPBDAT = 0x180; //hugerat
+
+    //int board_init (void)设置完成后，LED1和LED2会亮起！
+
+#endif
+/*---------------------------------------------------*/
+ return 0;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
diff -Nurp u-boot-2008.10/board/hugerat/rat2410/u-boot.lds u-boot-rat/board/hugerat/rat2410/u-boot.lds
--- u-boot-2008.10/board/hugerat/rat2410/u-boot.lds 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-rat/board/hugerat/rat2410/u-boot.lds 2008-10-19 03:30:31.000000000 +0800
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text      :
+ {
+   cpu/arm920t/start.o (.text)
+   *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss (NOLOAD) : { *(.bss) }
+ _end = .;
+}
diff -Nurp u-boot-2008.10/board/hugerat/rat2440/config.mk u-boot-rat/board/hugerat/rat2440/config.mk
--- u-boot-2008.10/board/hugerat/rat2440/config.mk 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-rat/board/hugerat/rat2440/config.mk 2008-12-16 16:32:08.000000000 +0800
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+#
+
+#
+# SMDK2410 has 1 bank of 64 MB DRAM
+#
+# 3000'0000 to 3400'0000
+#
+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
+# optionally with a ramdisk at 3080'0000
+#
+# we load ourself to 33F8'0000
+#
+# download area is 3300'0000
+#
+
+
+TEXT_BASE = 0x33f80000
diff -Nurp u-boot-2008.10/board/hugerat/rat2440/flash.c u-boot-rat/board/hugerat/rat2440/flash.c
--- u-boot-2008.10/board/hugerat/rat2440/flash.c 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-rat/board/hugerat/rat2440/flash.c 2008-10-19 03:30:31.000000000 +0800
@@ -0,0 +1,433 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush (void);
+
+
+#define FLASH_BANK_SIZE PHYS_FLASH_SIZE
+#define MAIN_SECT_SIZE 0x10000 /* 64 KB */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY  0x000000F0
+#define CMD_UNLOCK1  0x000000AA
+#define CMD_UNLOCK2  0x00000055
+#define CMD_ERASE_SETUP  0x00000080
+#define CMD_ERASE_CONFIRM 0x00000030
+#define CMD_PROGRAM  0x000000A0
+#define CMD_UNLOCK_BYPASS 0x00000020
+
+#define MEM_FLASH_ADDR1  (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
+#define MEM_FLASH_ADDR2  (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
+
+#define BIT_ERASE_DONE  0x00000080
+#define BIT_RDY_MASK  0x00000080
+#define BIT_PROGRAM_ERROR 0x00000020
+#define BIT_TIMEOUT  0x80000000 /* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+ int i, j;
+ ulong size = 0;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+  ulong flashbase = 0;
+
+  flash_info[i].flash_id =
+#if defined(CONFIG_AMD_LV400)
+   (AMD_MANUFACT & FLASH_VENDMASK) |
+   (AMD_ID_LV400B & FLASH_TYPEMASK);
+#elif defined(CONFIG_AMD_LV800)
+   (AMD_MANUFACT & FLASH_VENDMASK) |
+   (AMD_ID_LV800B & FLASH_TYPEMASK);
+#else
+#error "Unknown flash configured"
+#endif
+   flash_info[i].size = FLASH_BANK_SIZE;
+  flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+  memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+  if (i == 0)
+   flashbase = PHYS_FLASH_1;
+  else
+   panic ("configured too many flash banks!/n");
+  for (j = 0; j < flash_info[i].sector_count; j++) {
+   if (j <= 3) {
+    /* 1st one is 16 KB */
+    if (j == 0) {
+     flash_info[i].start[j] =
+      flashbase + 0;
+    }
+
+    /* 2nd and 3rd are both 8 KB */
+    if ((j == 1) || (j == 2)) {
+     flash_info[i].start[j] =
+      flashbase + 0x4000 + (j -
+              1) *
+      0x2000;
+    }
+
+    /* 4th 32 KB */
+    if (j == 3) {
+     flash_info[i].start[j] =
+      flashbase + 0x8000;
+    }
+   } else {
+    flash_info[i].start[j] =
+     flashbase + (j - 3) * MAIN_SECT_SIZE;
+   }
+  }
+  size += flash_info[i].size;
+ }
+
+ flash_protect (FLAG_PROTECT_SET,
+         CFG_FLASH_BASE,
+         CFG_FLASH_BASE + monitor_flash_len - 1,
+         &flash_info[0]);
+
+ flash_protect (FLAG_PROTECT_SET,
+         CONFIG_ENV_ADDR,
+         CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case (AMD_MANUFACT & FLASH_VENDMASK):
+  printf ("AMD: ");
+  break;
+ default:
+  printf ("Unknown Vendor ");
+  break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case (AMD_ID_LV400B & FLASH_TYPEMASK):
+  printf ("1x Amd29LV400BB (4Mbit)/n");
+  break;
+ case (AMD_ID_LV800B & FLASH_TYPEMASK):
+  printf ("1x Amd29LV800BB (8Mbit)/n");
+  break;
+ default:
+  printf ("Unknown Chip Type/n");
+  goto Done;
+  break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors/n",
+  info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++) {
+  if ((i % 5) == 0) {
+   printf ("/n   ");
+  }
+  printf (" %08lX%s", info->start[i],
+   info->protect[i] ? " (RO)" : "     ");
+ }
+ printf ("/n");
+
+      Done:;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ ushort result;
+ int iflag, cflag, prot, sect;
+ int rc = ERR_OK;
+ int chip;
+
+ /* first look for protection bits */
+
+ if (info->flash_id == FLASH_UNKNOWN)
+  return ERR_UNKNOWN_FLASH_TYPE;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+  return ERR_INVAL;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) !=
+     (AMD_MANUFACT & FLASH_VENDMASK)) {
+  return ERR_UNKNOWN_FLASH_VENDOR;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+  if (info->protect[sect]) {
+   prot++;
+  }
+ }
+ if (prot)
+  return ERR_PROTECTED;
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ cflag = icache_status ();
+ icache_disable ();
+ iflag = disable_interrupts ();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+  printf ("Erasing sector %2d ... ", sect);
+
+  /* arm simple, non interrupt dependent timer */
+  reset_timer_masked ();
+
+  if (info->protect[sect] == 0) { /* not protected */
+   vu_short *addr = (vu_short *) (info->start[sect]);
+
+   MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+   MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+   MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+   MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+   MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+   *addr = CMD_ERASE_CONFIRM;
+
+   /* wait until flash is ready */
+   chip = 0;
+
+   do {
+    result = *addr;
+
+    /* check timeout */
+    if (get_timer_masked () >
+        CFG_FLASH_ERASE_TOUT) {
+     MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+     chip = TMO;
+     break;
+    }
+
+    if (!chip
+        && (result & 0xFFFF) & BIT_ERASE_DONE)
+     chip = READY;
+
+    if (!chip
+        && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
+     chip = ERR;
+
+   } while (!chip);
+
+   MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+   if (chip == ERR) {
+    rc = ERR_PROG_ERROR;
+    goto outahere;
+   }
+   if (chip == TMO) {
+    rc = ERR_TIMOUT;
+    goto outahere;
+   }
+
+   printf ("ok./n");
+  } else { /* it was protected */
+
+   printf ("protected!/n");
+  }
+ }
+
+ if (ctrlc ())
+  printf ("User Interrupt!/n");
+
+      outahere:
+ /* allow flash to settle - wait 10 ms */
+ udelay_masked (10000);
+
+ if (iflag)
+  enable_interrupts ();
+
+ if (cflag)
+  icache_enable ();
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_hword (flash_info_t * info, ulong dest, ushort data)
+{
+ vu_short *addr = (vu_short *) dest;
+ ushort result;
+ int rc = ERR_OK;
+ int cflag, iflag;
+ int chip;
+
+ /*
+ * Check if Flash is (sufficiently) erased
+ */
+ result = *addr;
+ if ((result & data) != data)
+  return ERR_NOT_ERASED;
+
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ cflag = icache_status ();
+ icache_disable ();
+ iflag = disable_interrupts ();
+
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+ MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
+ *addr = CMD_PROGRAM;
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ /* wait until flash is ready */
+ chip = 0;
+ do {
+  result = *addr;
+
+  /* check timeout */
+  if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+   chip = ERR | TMO;
+   break;
+  }
+  if (!chip && ((result & 0x80) == (data & 0x80)))
+   chip = READY;
+
+  if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
+   result = *addr;
+
+   if ((result & 0x80) == (data & 0x80))
+    chip = READY;
+   else
+    chip = ERR;
+  }
+
+ } while (!chip);
+
+ *addr = CMD_READ_ARRAY;
+
+ if (chip == ERR || *addr != data)
+  rc = ERR_PROG_ERROR;
+
+ if (iflag)
+  enable_interrupts ();
+
+ if (cflag)
+  icache_enable ();
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ int l;
+ int i, rc;
+ ushort data;
+
+ wp = (addr & ~1); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+  data = 0;
+  for (i = 0, cp = wp; i < l; ++i, ++cp) {
+   data = (data >> 8) | (*(uchar *) cp << 8);
+  }
+  for (; i < 2 && cnt > 0; ++i) {
+   data = (data >> 8) | (*src++ << 8);
+   --cnt;
+   ++cp;
+  }
+  for (; cnt == 0 && i < 2; ++i, ++cp) {
+   data = (data >> 8) | (*(uchar *) cp << 8);
+  }
+
+  if ((rc = write_hword (info, wp, data)) != 0) {
+   return (rc);
+  }
+  wp += 2;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 2) {
+  data = *((vu_short *) src);
+  if ((rc = write_hword (info, wp, data)) != 0) {
+   return (rc);
+  }
+  src += 2;
+  wp += 2;
+  cnt -= 2;
+ }
+
+ if (cnt == 0) {
+  return ERR_OK;
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+  data = (data >> 8) | (*src++ << 8);
+  --cnt;
+ }
+ for (; i < 2; ++i, ++cp) {
+  data = (data >> 8) | (*(uchar *) cp << 8);
+ }
+
+ return write_hword (info, wp, data);
+}
diff -Nurp u-boot-2008.10/board/hugerat/rat2440/lowlevel_init.S u-boot-rat/board/hugerat/rat2440/lowlevel_init.S
--- u-boot-2008.10/board/hugerat/rat2440/lowlevel_init.S 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-rat/board/hugerat/rat2440/lowlevel_init.S 2008-12-10 19:08:15.000000000 +0800
@@ -0,0 +1,191 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+/*
+ *
+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
+ *
+ * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
+ *
+ */
+
+#define BWSCON 0x48000000
+
+/* BWSCON */
+#define DW8   (0x0)
+#define DW16   (0x1)
+#define DW32   (0x2)
+#define WAIT   (0x1<<2)
+#define UBLB   (0x1<<3)
+
+#define B1_BWSCON  (DW32)
+#define B2_BWSCON  (DW16)
+#define B3_BWSCON  (DW16 + WAIT + UBLB)
+/*by hugerat,phase 4-----------*/
+//#define B4_BWSCON  (DW16)
+#define B4_BWSCON  (DW16 + WAIT + UBLB)
+/*-----------------------------*/
+#define B5_BWSCON  (DW16)
+#define B6_BWSCON  (DW32)
+#define B7_BWSCON  (DW32)
+
+/* BANK0CON */
+#define B0_Tacs   0x0 /* 0clk */
+#define B0_Tcos   0x0 /* 0clk */
+#define B0_Tacc   0x7 /* 14clk */
+#define B0_Tcoh   0x0 /* 0clk */
+#define B0_Tah   0x0 /* 0clk */
+#define B0_Tacp   0x0
+#define B0_PMC   0x0 /* normal */
+
+/* BANK1CON */
+#define B1_Tacs   0x0 /* 0clk */
+#define B1_Tcos   0x0 /* 0clk */
+#define B1_Tacc   0x7 /* 14clk */
+#define B1_Tcoh   0x0 /* 0clk */
+#define B1_Tah   0x0 /* 0clk */
+#define B1_Tacp   0x0
+#define B1_PMC   0x0
+
+#define B2_Tacs   0x0
+#define B2_Tcos   0x0
+#define B2_Tacc   0x7
+#define B2_Tcoh   0x0
+#define B2_Tah   0x0
+#define B2_Tacp   0x0
+#define B2_PMC   0x0
+
+#define B3_Tacs   0x0 /* 0clk */
+#define B3_Tcos   0x3 /* 4clk */
+#define B3_Tacc   0x7 /* 14clk */
+#define B3_Tcoh   0x1 /* 1clk */
+#define B3_Tah   0x0 /* 0clk */
+#define B3_Tacp   0x3     /* 6clk */
+#define B3_PMC   0x0 /* normal */
+
+/*by hugerat,phase 4----------------*/
+//#define B4_Tacs   0x0 /* 0clk */
+//#define B4_Tcos   0x0 /* 0clk */
+//#define B4_Tacc   0x7 /* 14clk */
+//#define B4_Tcoh   0x0 /* 0clk */
+//#define B4_Tah   0x0 /* 0clk */
+//#define B4_Tacp   0x0
+//#define B4_PMC   0x0 /* normal */
+
+#define B4_Tacs   0x0 /* 0clk */
+#define B4_Tcos   0x3 /* 4clk */
+#define B4_Tacc   0x7 /* 14clk */
+#define B4_Tcoh   0x1 /* 1clk */
+#define B4_Tah   0x3 /* 4clk */
+#define B4_Tacp   0x6 /* 6clk */
+#define B4_PMC   0x0 /* normal */
+/*----------------------------------*/
+#define B5_Tacs   0x0 /* 0clk */
+#define B5_Tcos   0x0 /* 0clk */
+#define B5_Tacc   0x7 /* 14clk */
+#define B5_Tcoh   0x0 /* 0clk */
+#define B5_Tah   0x0 /* 0clk */
+#define B5_Tacp   0x0
+#define B5_PMC   0x0 /* normal */
+
+#define B6_MT   0x3 /* SDRAM */
+#define B6_Trcd   0x1
+#define B6_SCAN   0x1 /* 9bit */
+
+#define B7_MT   0x3 /* SDRAM */
+#define B7_Trcd   0x1 /* 3clk */
+#define B7_SCAN   0x1 /* 9bit */
+
+/*by hugerat ,phase 1-------------------------*/
+/* REFRESH parameter */
+#define REFEN   0x1 /* Refresh enable */
+#define TREFMD   0x0 /* CBR(CAS before RAS)/Auto refresh */
+//#define Trp   0x0 /* 2clk */
+#define Trc   0x3 /* 7clk */
+#define Tchr   0x2 /* 3clk */
+//#define REFCNT   1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+/**************************************/
+
+
+# if defined(CONFIG_S3C2440)
+#define Trp            0x2    /* 4clk */
+#define REFCNT            1012
+#else
+#define Trp            0x0    /* 2clk */
+#define REFCNT            0x0459
+#endif
+/*-------------------------------------*/
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+ /* memory control configuration */
+ /* make r0 relative the current location so that it */
+ /* reads SMRDATA out of FLASH rather than memory ! */
+
+ ldr     r0, =SMRDATA
+ ldr r1, _TEXT_BASE
+ sub r0, r0, r1
+ ldr r1, =BWSCON /* Bus Width Status Controller */
+ add     r2, r0, #13*4
+0:
+ ldr     r3, [r0], #4
+ str     r3, [r1], #4
+ cmp     r2, r0
+ bne     0b
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+/* the literal pools origin */
+
+SMRDATA:
+    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+

(B7_BWSCON<<28))
+    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32
+    .word 0x30
+    .word 0x30
diff -Nurp u-boot-2008.10/board/hugerat/rat2440/Makefile u-boot-rat/board/hugerat/rat2440/Makefile
--- u-boot-2008.10/board/hugerat/rat2440/Makefile 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-rat/board/hugerat/rat2440/Makefile 2008-12-11 13:53:16.000000000 +0800
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := rat2440.o nand_read.o flash.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff -Nurp u-boot-2008.10/board/hugerat/rat2440/nand_read.c u-boot-rat/board/hugerat/rat2440/nand_read.c
--- u-boot-2008.10/board/hugerat/rat2440/nand_read.c 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-rat/board/hugerat/rat2440/nand_read.c 2008-02-29 23:23:10.000000000 +0800
@@ -0,0 +1,111 @@
+#include <config.h>
+
+#define __REGb(x) (*(volatile unsigned char *)(x))
+#define __REGi(x) (*(volatile unsigned int *)(x))
+#define NF_BASE 0x4e000000
+
+
+#if defined(CONFIG_S3C2440)
+
+#define NFCONF __REGi(NF_BASE + 0x0)
+#define NFCONT __REGi(NF_BASE + 0x4)
+#define NFCMD __REGb(NF_BASE + 0x8)
+#define NFADDR __REGb(NF_BASE + 0xC)
+#define NFDATA __REGb(NF_BASE + 0x10)
+#define NFSTAT __REGb(NF_BASE + 0x20)
+
+//#define GPDAT       __REGi(GPIO_CTL_BASE+oGPIO_F+oGPIO_DAT)
+
+#define NAND_CHIP_ENABLE (NFCONT &= ~(1<<1))
+#define NAND_CHIP_DISABLE (NFCONT |= (1<<1))
+#define NAND_CLEAR_RB (NFSTAT |= (1<<2))
+#define NAND_DETECT_RB { while(! (NFSTAT&(1<<2)));}
+
+#define BUSY 4
+inline void wait_idle(void) {
+ while(!(NFSTAT & BUSY));
+ NFSTAT |= BUSY;
+}
+
+#define NAND_SECTOR_SIZE 512
+#define NAND_BLOCK_MASK (NAND_SECTOR_SIZE - 1)
+
+/* low level nand read function */
+int
+nand_read_ll(unsigned char *buf, unsigned long start_addr, int size)
+{
+ int i, j;
+
+ if ((start_addr & NAND_BLOCK_MASK) || (size & NAND_BLOCK_MASK)) {
+ return -1; /* invalid alignment */
+ }
+
+ NAND_CHIP_ENABLE;
+
+ for(i=start_addr; i < (start_addr + size);) {
+ /* READ0 */
+  NAND_CLEAR_RB;
+  NFCMD = 0;
+
+  /* Write Address */
+  NFADDR = i & 0xff;
+  NFADDR = (i >> 9) & 0xff;
+  NFADDR = (i >> 17) & 0xff;
+  NFADDR = (i >> 25) & 0xff;
+
+  NAND_DETECT_RB;
+
+  for(j=0; j < NAND_SECTOR_SIZE; j++, i++) {
+  *buf = (NFDATA & 0xff);
+  buf++;
+  }
+ }
+ NAND_CHIP_DISABLE;
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_S3C2410)
+
+#define NFCONF __REGi(NF_BASE + 0x0)
+#define NFCMD __REGb(NF_BASE + 0x4)
+#define NFADDR __REGb(NF_BASE + 0x8)
+#define NFDATA __REGb(NF_BASE + 0xc)
+#define NFSTAT __REGb(NF_BASE + 0x10)
+#define BUSY 1
+
+inline void wait_idle(void) {
+ int i;
+ while(!(NFSTAT & BUSY))
+ for(i=0; i<10; i++);
+}
+/* low level nand read function */
+int
+nand_read_ll(unsigned char *buf, unsigned long start_addr, int size)
+{
+ int i, j;
+ if ((start_addr & NAND_BLOCK_MASK) || (size & NAND_BLOCK_MASK)) {
+ return -1; /* invalid alignment */
+ }
+ /* chip Enable */
+ NFCONF &= ~0x800;
+ for(i=0; i<10; i++);
+ for(i=start_addr; i < (start_addr + size);) {
+ /* READ0 */
+ NFCMD = 0;
+ /* Write Address */
+ NFADDR = i & 0xff;
+ NFADDR = (i >> 9) & 0xff;
+ NFADDR = (i >> 17) & 0xff;
+ NFADDR = (i >> 25) & 0xff;
+ wait_idle();
+ for(j=0; j < NAND_SECTOR_SIZE; j++, i++) {
+ *buf = (NFDATA & 0xff);
+ buf++;
+ }
+ }
+ /* chip Disable */
+ NFCONF |= 0x800; /* chip disable */
+ return 0;
+}
+#endif
diff -Nurp u-boot-2008.10/board/hugerat/rat2440/rat2440.c u-boot-rat/board/hugerat/rat2440/rat2440.c
--- u-boot-2008.10/board/hugerat/rat2440/rat2440.c 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-rat/board/hugerat/rat2440/rat2440.c 2008-12-11 16:57:57.000000000 +0800
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <s3c2410.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FCLK_SPEED 1
+
+#if FCLK_SPEED==0  /* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV 0xC3
+#define M_PDIV 0x4
+#define M_SDIV 0x1
+#elif FCLK_SPEED==1  /* Fout = 202.8MHz */
+/*by hugerat ,phase 1-------------*/
+#if defined(CONFIG_S3C2410)
+/* Fout = 202.8MHz */
+#define M_MDIV    0xA1
+#define M_PDIV    0x3
+#define M_SDIV    0x1
+#endif
+
+#if defined(CONFIG_S3C2440)
+/* Fout = 405MHz */
+#define M_MDIV 0x7f
+#define M_PDIV 0x2
+#define M_SDIV 0x1
+#endif
+
+/*#define M_MDIV 0xA1
+#define M_PDIV 0x3
+#define M_SDIV 0x1*/
+/*------------------------*/
+#endif
+
+#define USB_CLOCK 1
+
+#if USB_CLOCK==0
+#define U_M_MDIV 0xA1
+#define U_M_PDIV 0x3
+#define U_M_SDIV 0x1
+#elif USB_CLOCK==1
+/*by hugerat ,phase 1-----*/
+#if defined(CONFIG_S3C2410)
+#define U_M_MDIV    0x48
+#define U_M_PDIV    0x3
+#endif
+
+#if defined(CONFIG_S3C2440)
+#define U_M_MDIV 0x38
+#define U_M_PDIV 0x2
+#endif
+
+/*#define U_M_MDIV 0x48
+#define U_M_PDIV 0x3*/
+
+/*------------------------*/
+#define U_M_SDIV 0x2
+#endif
+
+static inline void delay (unsigned long loops)
+{
+ __asm__ volatile ("1:/n"
+   "subs %0, %1, #1/n"
+   "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+ /* to reduce PLL lock time, adjust the LOCKTIME register */
+ clk_power->LOCKTIME = 0xFFFFFF;
+
+ /* configure MPLL */
+ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ delay (4000);
+
+ /* configure UPLL */
+ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ delay (8000);
+
+ /* set up the I/O ports */
+ gpio->GPACON = 0x007FFFFF;
+/*by hugerat ,phase 1---------------*/
+#if defined(CONFIG_rat2440_LED)
+ gpio->GPBCON = 0x00055555;
+#else
+ gpio->GPBCON = 0x00044555;
+#endif
+
+ /*gpio->GPBCON = 0x00044555;*/
+/*-----------------------------------*/
+ gpio->GPBUP = 0x000007FF;
+ gpio->GPCCON = 0xAAAAAAAA;
+ gpio->GPCUP = 0x0000FFFF;
+ gpio->GPDCON = 0xAAAAAAAA;
+ gpio->GPDUP = 0x0000FFFF;
+ gpio->GPECON = 0xAAAAAAAA;
+ gpio->GPEUP = 0x0000FFFF;
+ gpio->GPFCON = 0x000055AA;
+ gpio->GPFUP = 0x000000FF;
+ gpio->GPGCON = 0xFF95FFBA;
+ gpio->GPGUP = 0x0000FFFF;
+ gpio->GPHCON = 0x002AFAAA;
+ gpio->GPHUP = 0x000007FF;
+/*by hugerat ,phase 1-----------------------------------*/
+#if defined(CONFIG_S3C2410)
+    /* arch number of SMDK2410-Board */
+    gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
+#endif
+
+#if defined(CONFIG_S3C2440)
+    /* arch number of S3C2440 -Board */
+    gd->bd->bi_arch_number = MACH_TYPE_mini2440 ;
+#endif
+
+ /* arch number of SMDK2410-Board */
+ //gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
+/*------------------------------------------------------*/
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x30000100;
+
+ icache_enable();
+ dcache_enable();
+/*by hugerat ,phase 1--------------------------------*/
+# if defined(CONFIG_rat2440_LED)
+    gpio->GPBDAT = 0x180; //hugerat
+
+    //int board_init (void)设置完成后，LED1和LED2会亮起！
+
+#endif
+/*---------------------------------------------------*/
+ return 0;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
diff -Nurp u-boot-2008.10/board/hugerat/rat2440/u-boot.lds u-boot-rat/board/hugerat/rat2440/u-boot.lds
--- u-boot-2008.10/board/hugerat/rat2440/u-boot.lds 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-rat/board/hugerat/rat2440/u-boot.lds 2008-10-19 03:30:31.000000000 +0800
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text      :
+ {
+   cpu/arm920t/start.o (.text)
+   *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss (NOLOAD) : { *(.bss) }
+ _end = .;
+}
diff -Nurp u-boot-2008.10/common/cmd_nand.c u-boot-rat/common/cmd_nand.c
--- u-boot-2008.10/common/cmd_nand.c 2008-10-19 03:30:31.000000000 +0800
+++ u-boot-rat/common/cmd_nand.c 2008-12-15 22:14:50.000000000 +0800
@@ -340,7 +340,24 @@ int do_nand(cmd_tbl_t * cmdtp, int flag,
    else
     ret = nand_write_skip_bad(nand, off, &size,
          (u_char *)addr);
-  } else if (s != NULL && !strcmp(s, ".oob")) {
+  }
+  /*by hugerat,phase 6-----------*/
+  else if(s != NULL && !strcmp(s, ".yaffs"))
+  {
+   if(read)
+     {
+    printf("nand read.yaffs is not provide!"); //不支持读取yaffs
+     }
+   else
+     {
+    nand->writeoob = 1;
+    ret = nand_write_skip_bad(nand,off,&size,(u_char *)addr); //写入yaffs
+    nand->writeoob = 0;
+     }
+
+  }
+  /*-----------------------------*/
+    else if (s != NULL && !strcmp(s, ".oob")) {
    /* out-of-band data */
    mtd_oob_ops_t ops = {
     .oobbuf = (u8 *)addr,
@@ -476,6 +493,11 @@ U_BOOT_CMD(nand, 5, 1, do_nand,
     "nand write - addr off|partition size/n"
     "    read/write 'size' bytes starting at offset 'off'/n"
     "    to/from memory address 'addr', skipping bad blocks./n"
+    /*by hugerat,phase6------------*/
+    "nand write.yaffs - addr off|partition size/n"
+    "    write 'size' bytes starting at offset 'off'/n"
+    "    to/from yaffs image in memory address 'addr', skipping bad blocks./n"
+    /*-----------------------------*/
     "nand erase [clean] [off size] - erase 'size' bytes from/n"
     "    offset 'off' (entire device if not specified)/n"
     "nand bad - show bad blocks/n"
diff -Nurp u-boot-2008.10/cpu/arm920t/s3c24x0/i2c.c u-boot-rat/cpu/arm920t/s3c24x0/i2c.c
--- u-boot-2008.10/cpu/arm920t/s3c24x0/i2c.c 2008-10-19 03:30:31.000000000 +0800
+++ u-boot-rat/cpu/arm920t/s3c24x0/i2c.c 2008-12-05 14:25:37.000000000 +0800
@@ -32,7 +32,10 @@

#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
+/*by hugerat,phase 1---------*/
+//#elif defined(CONFIG_S3C2410)
+#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+/*---------------------------*/
#include <s3c2410.h>
#endif
#include <i2c.h>
@@ -63,7 +66,10 @@ static int GetI2CSDA(void)
{
  S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();

-#ifdef CONFIG_S3C2410
+/*by hugerat,phase 1-------------*/
+//#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+/*-------------------------------*/
  return (gpio->GPEDAT & 0x8000) >> 15;
#endif
#ifdef CONFIG_S3C2400
@@ -82,7 +88,10 @@ static void SetI2CSCL(int x)
{
  S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();

-#ifdef CONFIG_S3C2410
+/*by hugerat,phase 1-------------*/
+//#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+/*-------------------------------*/
  gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
#endif
#ifdef CONFIG_S3C2400
@@ -139,7 +148,10 @@ void i2c_init (int speed, int slaveadd)
  }

  if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) {
-#ifdef CONFIG_S3C2410
+/*by hugerat,phase 1-------------*/
+//#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+/*-------------------------------*/
   ulong old_gpecon = gpio->GPECON;
#endif
#ifdef CONFIG_S3C2400
@@ -147,7 +159,10 @@ void i2c_init (int speed, int slaveadd)
#endif
   /* bus still busy probably by (most) previously interrupted transfer */

-#ifdef CONFIG_S3C2410
+/*by hugerat,phase 1-------------*/
+//#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+/*-------------------------------*/
   /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
   gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
#endif
@@ -171,7 +186,10 @@ void i2c_init (int speed, int slaveadd)
   udelay (1000);

   /* restore pin functions */
-#ifdef CONFIG_S3C2410
+/*by hugerat,phase 1-------------*/
+//#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+/*-------------------------------*/
   gpio->GPECON = old_gpecon;
#endif
#ifdef CONFIG_S3C2400
diff -Nurp u-boot-2008.10/cpu/arm920t/s3c24x0/interrupts.c u-boot-rat/cpu/arm920t/s3c24x0/interrupts.c
--- u-boot-2008.10/cpu/arm920t/s3c24x0/interrupts.c 2008-10-19 03:30:31.000000000 +0800
+++ u-boot-rat/cpu/arm920t/s3c24x0/interrupts.c 2008-12-16 11:03:20.000000000 +0800
@@ -30,12 +30,17 @@
*/

#include <common.h>
-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
-
+/*by hugerat, phase 1-------------*/
+//#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) || defined (CONFIG_S3C2440)
+/*--------------------------------*/
#include <arm920t.h>
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
+/*by hugerat ,phase -1 --------------*/
+//#elif defined(CONFIG_S3C2410)
+#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+/*-----------------------------------*/
#include <s3c2410.h>
#endif

@@ -176,9 +181,16 @@ ulong get_tbclk (void)

#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
  tbclk = timer_load_val * 100;
+/*by hugerat, phase 1----------------*/
+//#elif defined(CONFIG_SBC2410X) || /
+ //    defined(CONFIG_SMDK2410) || /
+    // defined(CONFIG_VCMA9)
#elif defined(CONFIG_SBC2410X) || /
       defined(CONFIG_SMDK2410) || /
-      defined(CONFIG_VCMA9)
+      defined(CONFIG_VCMA9)    || /
+      defined(CONFIG_rat2440) || /
+      defined(CONFIG_rat2410)
+/*------------------------------------*/
  tbclk = CFG_HZ;
#else
# error "tbclk not configured"
diff -Nurp u-boot-2008.10/cpu/arm920t/s3c24x0/nand.c u-boot-rat/cpu/arm920t/s3c24x0/nand.c
--- u-boot-2008.10/cpu/arm920t/s3c24x0/nand.c 2008-10-19 03:30:31.000000000 +0800
+++ u-boot-rat/cpu/arm920t/s3c24x0/nand.c 2008-12-16 10:55:28.000000000 +0800
@@ -36,6 +36,9 @@
#define __REGb(x) (*(volatile unsigned char *)(x))
#define __REGi(x) (*(volatile unsigned int *)(x))

+/*by hugerat,phase3 -----------------------*/
+#if defined(CONFIG_S3C2410)
+
#define NF_BASE  0x4e000000
#define NFCONF  __REGi(NF_BASE + 0x0)
#define NFCMD  __REGb(NF_BASE + 0x4)
@@ -45,6 +48,34 @@
#define NFECC0  __REGb(NF_BASE + 0x14)
#define NFECC1  __REGb(NF_BASE + 0x15)
#define NFECC2  __REGb(NF_BASE + 0x16)
+#else
+#if defined(CONFIG_S3C2440)
+
+#define NF_BASE  0x4e000000
+#define NFCONF  __REGi(NF_BASE + 0x0)
+#define NFCONT  __REGi(NF_BASE + 0x4)
+#define NFCMD  __REGb(NF_BASE + 0x8)
+#define NFADDR  __REGb(NF_BASE + 0xc)
+#define NFDATA  __REGb(NF_BASE + 0x10)
+#define NFMECCD0 __REGi(NF_BASE + 0x14)
+#define NFMECCD1 __REGi(NF_BASE + 0x18)
+#define NFSECCD  __REGi(NF_BASE + 0x1C)
+#define NFSTAT  __REGb(NF_BASE + 0x20)
+#define NFSTAT0  __REGi(NF_BASE + 0x24)
+#define NFSTAT1  __REGi(NF_BASE + 0x28)
+#define NFMECC0  __REGi(NF_BASE + 0x2C)
+#define NFMECC1  __REGi(NF_BASE + 0x30)
+#define NFSECC  __REGi(NF_BASE + 0x34)
+#define NFSBLK  __REGi(NF_BASE + 0x38)
+#define NFEBLK  __REGi(NF_BASE + 0x3c)
+
+#define S3C2440_NFCONT_nCE (1<<1)
+#define S3C2440_ADDR_NALE 0x0c
+#define S3C2440_ADDR_NCLE 0x08
+
+#endif
+#endif
+/*------------------------------------------*/

#define S3C2410_NFCONF_EN          (1<<15)
#define S3C2410_NFCONF_512BYTE     (1<<14)
@@ -58,21 +89,23 @@
#define S3C2410_ADDR_NALE 4
#define S3C2410_ADDR_NCLE 8

+ulong IO_ADDR_W = NF_BASE; //by hugerat,phase3
+
static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
  struct nand_chip *chip = mtd->priv;
-
+
  DEBUGN("hwcontrol(): 0x%02x 0x%02x/n", cmd, ctrl);
-
+#if defined(CONFIG_S3C2410)
  if (ctrl & NAND_CTRL_CHANGE) {
-  ulong IO_ADDR_W = NF_BASE;
-
+  //ulong IO_ADDR_W = NF_BASE; by hugerat.phase3
+  IO_ADDR_W = NF_BASE;
   if (!(ctrl & NAND_CLE))
    IO_ADDR_W |= S3C2410_ADDR_NCLE;
   if (!(ctrl & NAND_ALE))
    IO_ADDR_W |= S3C2410_ADDR_NALE;

-  chip->IO_ADDR_W = (void *)IO_ADDR_W;
+  //chip->IO_ADDR_W = (void *)IO_ADDR_W; //by hugerat,phase3

   if (ctrl & NAND_NCE)
    NFCONF &= ~S3C2410_NFCONF_nFCE;
@@ -81,7 +114,39 @@ static void s3c2410_hwcontrol(struct mtd
  }

  if (cmd != NAND_CMD_NONE)
-  writeb(cmd, chip->IO_ADDR_W);
+  /*by hugerat,phase3--------*/
+  //writeb(cmd, chip->IO_ADDR_W);
+  writeb(cmd,(void *)IO_ADDR_W);
+#endif
+/*by hugerat,phase3----------*/
+#if defined(CONFIG_S3C2440)
+ if (ctrl & NAND_CTRL_CHANGE) {
+  IO_ADDR_W = NF_BASE; //by hugerat,phase3
+  if