AT89C51-科技外文文献

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信息与控制

英文原文

Description

The AT89C51is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes ofFlash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. Thedevice is manufactured using Atmel’s high density nonvolatile memory technologyand is compatible with the industry standard MCS-51™ instruction set andpinout. The chip combines a versatile 8-bit CPU with Flash on a monolithicchip, the Atmel AT89C51 is a powerful microcomputer which provides a highlyflexible and cost effective solution to many embedded control applications.

Features:

• Compatiblewith MCS-51™ Products

• 4K Bytes ofIn-System Reprogrammable Flash Memory

• Endurance:1,000 Write/Erase Cycles

• FullyStatic Operation: 0 Hz to 24 MHz

• Three-LevelProgram Memory Lock

• 128 x 8-BitInternal RAM

• 32Programmable I/O Lines

• Two 16-BitTimer/Counters

• SixInterrupt Sources

•Programmable Serial Channel

• Low PowerIdle and Power Down Modes

TheAT89C51 provides the following standard features: 4K bytes of Flash, 128 bytesof RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-levelinterrupt architecture, a full duplex serial port, on-chip oscillator and clockcircuitry. In addition, the AT89C51 is designed with static logic for operationdown to zero frequency and supports two software selectable power saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial portand interrupt system to continue functioning. The Power Down Mode saves the RAMcontents but freezes the oscillator disabling all other chip functions untilthe next hardware reset.

Block Diagram

PinDescription:

VCC Supplyvoltage.

GND Ground.

Port 0

Port0 is an 8-bit open drain bidirectional I/O port. As an output port each pin cansink eight TTL inputs. When is are written to port 0 pins, the pins can be usedas high impedance inputs.

Port0 may also be configured to be the multiplexed loworder address/data bus duringaccesses to external program and data memory. In this mode P0 has internalpullups.

Port0 also receives the code bytes during Flash programming, and outputs the codebytes during program verification. External pullups are required during programverification.

Port 1

Port1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 outputbuffers can sink/source four TTL inputs. When 1s are written to Port 1 pinsthey are pulled high by the internal pullups and can be used as inputs. Asinputs, Port 1 pins that are externally being pulled low will source current(IIL) because of the internal pullups.

Port1 also receives the low-order address bytes during Flash programming andverification.

Port 2

Port2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 outputbuffers can sink/source four TTL inputs. When 1s are written to Port 2 pinsthey are pulled high by the internal pullups and can be used as inputs. Asinputs, Port 2 pins that are externally being pulled low will source current (IIL)because of the internal pullups.

Port 2 emits the high-order address byteduring fetches from external program memory and during accesses to externaldata memory that use 16-bit addresses (MOVX @ DPTR). In this application ituses strong internal pull-ups when emitting 1s. During accesses to externaldata memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents ofthe P2 Special Function Register.

Port2 also receives the high-order address bits and some control signals duringFlash programming and verification.

Port 3

Port3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 outputbuffers can sink/source four TTL inputs. When 1s are written to Port 3 pinsthey are pulled high by the internal pullups and can be used as inputs. Asinputs, Port 3 pins that are externally being pulled low will source current(IIL) because of the pullups.

Port 3 also serves the functions of variousspecial features of the AT89C51 as listed below:

Port pin

alternate functions

P3.0

rxd (serial input port)

P3.1

txd (serial output port)

P3.2

^int0 (external interrupt0)

P3.3

^int1 (external interrupt1)

P3.4

t0 (timer0 external input)

P3.5

t1 (timer1 external input)

P3.6

^WR (external data memory write strobe)

P3.7

^rd (external data memory read strobe)

Port3 also receives some control signals for Flash programming and verification.

RST

Resetinput. A high on this pin for two machine cycles while the oscillator isrunning resets the device.

ALE/PROG

AddressLatch Enable output pulse for latching the low byte of the address duringaccesses to external memory. This pin is also the program pulse input (PROG)during Flash programming.

Innormal operation ALE is emitted at a constant rate of 1/6 the oscillatorfrequency, and may be used for external timing or clocking purposes. Note,however, that one ALE pulse is skipped during each access to external DataMemory.

Ifdesired, ALE operation can be disabled by setting bit 0 of SFR location 8EH.With the bit set, ALE is active only during a MOVX or MOVC instruction.Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has noeffect if the microcontroller is in external execution mode.

PSEN

ProgramStore Enable is the read strobe to external program memory.

Whenthe AT89C51 is executing code from external program memory, PSEN is activatedtwice each machine cycle, except that two PSEN activations are skipped duringeach access to external data memory.

EA/VPP

ExternalAccess Enable. EA must be strapped to GND in order to enable the device tofetch code from external program memory locations starting at 0000H up toFFFFH. Note, however, that if lock bit 1 is programmed, EA will be internallylatched on reset.

EAshould be strapped to VCC for internal program executions.

Thispin also receives the 12-volt programming enable voltage(VPP) during Flash programming,for parts that require 12-volt VPP.

XTAL1

Inputto the inverting oscillator amplifier and input to the internal clock operatingcircuit.

XTAL2

Outputfrom the inverting oscillator amplifier.

OscillatorCharacteristics

XTAL1 andXTAL2 are the input and output, respectively, of an inverting amplifier whichcan be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the devicefrom an external clock source, XTAL2 should be left unconnected while XTAL1 isdriven as shown in Figure 2. There are no requirements on the duty cycle of theexternal clock signal, since the input to the internal clocking circuitry isthrough a divide-by-two flip-flop, but minimum and maximum voltage high and lowtime specifications must be observed.

Idle Mode

Inidle mode, the CPU puts itself to sleep while all the onchip peripherals remainactive. The mode is invoked by software. The content of the on-chip RAM and allthe special functions registers remain unchanged during this mode. The idlemode can be terminated by any enabled interrupt or by a hardware reset.

Itshould be noted that when idle is terminated by a hard ware reset, the devicenormally resumes program execution, from where it left off, up to two machinecycles before the internal reset algorithm takes control. On-chip hardwareinhibits access to internal RAM in this event, but access to the port pins isnot inhibited. To eliminate the possibility of an unexpected write to a port pinwhen Idle is terminated by reset, the instruction following the one thatinvokes Idle should not be one that writes to a port pin or to external memory.

Status of External Pins During Idle andPower Down Modes

mode

Program memory

ALE

^psen

Port0

Port1

Port2

Port3

idle

internal

data

Data

Idle

External

float

Data

data

Data

Power down

Internal

Data

Power down

External

float

data

Data

data

Power Down Mode

Inthe power down mode the oscillator is stopped, and the instruction that invokespower down is the last instruction executed. The on-chip RAM and SpecialFunction Registers retain their values until the power down mode is terminated.The only exit from power down is a hardware reset. Reset redefines the SFRs butdoes not change the on-chip RAM. The reset should not be activated before VCCis restored to its normal operating level and must be held active long enoughto allow the oscillator to restart and stabilize.

ProgramMemory Lock Bits

Onthe chip are three lock bits which can be left unprogrammed (U) or can beprogrammed (P) to obtain the additional features listed in the table below:

LockBit Protection Modes

Program lock bits

Protection type

Lb1

Lb2

Lb3

No program lock features

Movc instructions executed from external program memory are disable from fetching code bytes from internal memory, ^ea is sampled and latched on reset, and further programming of the flash disabled

Same as mode 2, also verify is disable.

Same as mode 3, also external execution is disabled.

Whenlock bit 1 is programmed, the logic level at the EA pin is sampled and latchedduring reset. If the device is powered up without a reset, the latchinitializes to a random value, and holds that value until reset is activated.It is necessary that the latched value of EA be in agreement with the currentlogic level at that pin in order for the device to function properly.

Programmingthe Flash：

TheAT89C51 is normally shipped with the on-chip Flash memory array in the erasedstate (that is, contents = FFH) and ready to be programmed. Theprogramming interface accepts either a high-voltage (12-volt) or a low-voltage(VCC) program enable signal. The lowvoltage programming mode provides a convenient way to program the AT89C51inside the user’s system, while the high-voltage programming mode is compatiblewith conventional third party Flash or EPROM programmers.

TheAT89C51 is shipped with either the high-voltage or low-voltage programming modeenabled. The respective top-side marking and device signature codes are listedin the following table.

Vpp=12v

Vpp=5v

Top-side mark

AT89C51

xxxx

yyww

AT89C51

xxxx-5

yyww

signature

(030H)=1EH

(031H)=51H

(032H)=FFH

(030H)=1EH

(031H)=51H

(032H)=05H

TheAT89C51 code memory array is programmed byte-bybyte in either programming mode.To program any nonblank byte in the on-chip Flash Programmable and ErasableRead Only Memory, the entire memory must be erased using the Chip Erase Mode.

ProgrammingAlgorithm:

Beforeprogramming the AT89C51, the address, data and control signals should be set upaccording to the Flash programming mode table and Figures 3 and 4. To programthe AT89C51, take the following steps.

1.Input the desired memory location on the address lines.

2.Input the appropriate data byte on the data lines.

3.Activate the correct combination of control signals.

4.Raise EA/VPP to 12V for the high-voltage programming mode.

5.Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. Thebyte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeatsteps 1 through 5, changing the address and data for the entire array or untilthe end of the object file is reached.

Data Polling: TheAT89C51 features Data Polling to indicate the end of a write cycle. During awrite cycle, an attempted read of the last byte written will result in thecomplement of the written datum on PO.7. Once the write cycle has beencompleted, true data are valid on all outputs, and the next cycle may begin.Data Polling may begin any time after a write cycle has been initiated.

Ready/Busy: Theprogress of byte programming can also be monitored by the RDY/BSY outputsignal. P3.4 is pulled low after ALE goes high during programming to indicateBUSY. P3.4 is pulled high again when programming is done to indicate READY.

Program Verify:If lock bits LB1 and LB2 have not been programmed, the programmed code data canbe read back via the address and data lines for verification. The lock bitscannot be verified directly. Verification of the lock bits is achieved byobserving that their features are enabled.

Chip Erase: Theentire Flash Programmable and Erasable Read Only Memory array is erasedelectrically by using the proper combination of control signals and by holdingALE/PROG low for 10 ms. The code array is written with all “1”s. The chip eraseoperation must be executed before the code memory can be re-programmed.

Reading the Signature Bytes:The signature bytes are read by the same procedure as a normal verification oflocations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to alogic low. The values returned are as follows.

(030H)= 1EH indicates manufactured by Atmel

(031H)= 51H indicates 89C51

(032H)= FFH indicates 12V programming

(032H)= 05H indicates 5V programming

Programming Interface

Everycode byte in the Flash array can be written and the entire array can be erasedby using the appropriate combination of control signals. The write operationcycle is selftimed and once initiated, will automatically time itself tocompletion.

Table 1 Flash Programming Modes

mode

RST

^PSEN

ALE/^PROG

^EA/Vpp

P2.6

P2.7

P3.6

P3.7

Write code data

H/12V

Read code data

Write lock

Bit-1

H/12V

Bit-2

H/12V

Bit-3

H/12V

Chip erase

H/12V

Read signature syte

Note:1.chip erase requires a 10-ms PROG pulse

Figure3. Programming the Flash Figure 4. Verifying the Flash

FlashProgramming and Verification Characteristics

TA= 0°C to 70°C, VCC = 5.0 10%

Symbol

parameter

min

max

Units

Vpp⑴

Programming enable voltage

11.5

12.5

Ipp⑴

Programming enable current

1.0

1/Tclcl

Oscillator frequency

MHZ

Tavgl

Address setup to ^PSEN low

48Tclcl

Tghax

Address hole after ^PSEN

48Tclcl

Tdvgl

Data setup to ^PSEN low

48Tclcl

Tghdx

Data hole after ^PSEN

48Tclcl

Tehsh

P2.7(^enable)high to Vpp

48Tclcl

Tshgl

Vpp setup to ^PSEN low

Tghsl⑴

Vpp hole after ^PSEN

Tglgh

^PSEN width

110

Tavqv

Address to data valid

48Tclcl

Telqv

^enable low to data valid

48Tclcl

Tehqz

Data float after ^enable

48Tclcl

Tghbl

^PSEN high to ^busy low

1.0

Twc

Byte write cycle time

2.0

Note:1. Only used in 12-volt programming mode.

FlashProgramming and Verification Waveforms - High Voltage Mode (VPP = 12V)

FlashProgramming and Verification Waveforms - Low Voltage Mode (VPP = 5V)

AbsoluteMaximum Ratings*

OperatingTemperature.................................. -55°C to +125°C

StorageTemperature ..................................... -65°C to +150°C

Voltage onAny Pin

with Respectto Ground .....................................-1.0V to +7.0V

MaximumOperating Voltage............................................. 6.6V

DC OutputCurrent...................................................... 15.0 mA

DCCharacteristics

TA = -40°C to85°C, VCC = 5.0V 20% (unless otherwise noted)

symbol

parameter

condition

min

max

units

Vil

Input low voltage

(except ^EA)

-0.5

0.2Vcc-0.1

Vil1

Input low voltage(^EA)

-0.5

0.2Vcc-0.3

Vih

Input high voltage

Except XTAL1,XTAL2

0.2Vcc+0.9

Vcc+0.5

Vih1

Input high voltage

(XTAL1,RST)

0.7Vcc

Vcc+0.5

Vol

Output low voltage⑴(ports 1,2,3 )

Iol=1.6mA

0.45

Vol1

Output low voltage⑴(port0,ALE,^PSEN)

Ioh=3.2mA

0.45

Ioh=-60uA,Vcc=-5V+10%

2.4

Ioh=-25uA

0.75Vcc

Voh

Output high voltage⑴(ports 1,2,3 )

Ioh=-60uA,Vcc=5V+10%

0.9Vcc

Voh1

Output low voltage⑴(port0,ALE,^PSEN)

Ioh=-800UA,Vcc=5V+10%

2.4

Ioh=-300uA,

0.75Vcc

Ioh=-80uA

0.9Vcc

Iil

Logical 0 input current(ports 1,2,3)

Vin=0.45V

-50

Itl

Logical 1 to 0 transition current(ports 1,2,3)

Vin=2V,Vcc=5V+10%

-650

Ili

Input leakage current(port 0, ^EA)

0.45<Vin<Vcc

+10

RRST

Reset pulldown resistor

300

kom

Cio

Pin capacitance

Testfreq=1MHZ,TA=25℃

Icc

Power supply current

Active mode, 12MHZ

Idle mode,12MHZ

Power down mode⑵

Vcc=6V

100

Vcc=3V

Notes: 1.Under steady state (non-transient) conditions, IOL must be externally limitedas follows:

Maximum IOLper port pin: 10 mA

Maximum IOLper 8-bit port: Port 0: 26 mA

Ports 1, 2,3: 15 mA

Maximum totalIOL for all output pins: 71 mA

2. MinimumVCC for Power Down is 2V.

AC Characteristics

(UnderOperating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN = 100 pF;Load Capacitance for all other outputs = 80 pF)

ExternalProgram and Data Memory Characteristics

Symbol

Parameter

12MHzOscillator

16to 24 MHz Oscillator

Units

Min

Max

Min

Max

1/TCLCL

Oscillator Frequency

MHz

TLHLL

ALE Pulse Width

127

2TCLCL-40

TAVLL

Address Valid to ALE Low

TCLCL-13

TLLAX

Address Hold After ALE Low

TCLCL-20

TLLIV

ALE Low to Valid Instruction In

233

4TCLCL-65

TLLPL

ALE Low to PSEN Low

TCLCL-13

TPLPH

PSEN Pulse Width

205

3TCLCL-20

TPLIV

PSEN Low toValid Instruction In

145

3TCLCL-45

TPXIX

InputInstructionHold After PSEN

TPXIZ

InputInstructionFloat AfterPSEN

TCLCL-10

TPXAV

PSEN to Address Valid

TCLCL-8

TAVIV

Address to Valid Instruction In

312

5TCLCL-55

TPLAZ

PSEN Low to Address Float

TRLRH

RD Pulse Width

400

6TCLCL-100

TWLWH

WR Pulse Width

400

6TCLCL-100

TRLDV

RD Low to Valid Data In

252

5TCLCL-90

TRHDX

Data Hold After RD

TRHDZ

Data Float After RD

2TCLCL-28

TLLDV

ALE Low to Valid Data In

517

8TCLCL-150

TAVDV

Address to Valid Data In

585

9TCLCL-165

TLLWL

ALE Low to RD or WR Low

200

300

3TCLCL-50

3TCLCL+50

TAVWL

Address to RD or WR Low

203

4TCLCL-75

TQVWX

Data Valid to WR Transition

TCLCL-20

TQVWH

Data Valid to WR High

433

7TCLCL-120

TWHQX

Data Hold After WR

TCLCL-20

TRLAZ

RD Low to Address Float

TWHLH

RD or WR High to ALE High

123

TCLCL-20

TCLCL+25

ExternalProgram Memory Read Cycle

External DataMemory Read Cycle

External DataMemory Write Cycle

External Clock DriveWaveforms

External Clock Drive

符号

参数

最小值

最大值

单位

1/TCLCL

Oscillator Frequency

MHz

TCLCL

Clock Period

41.6

TCHCX

High Time

TCLCX

Low Time

TCLCH

Rise Time

TCHCL

Fall Time

Serial Port Timing: Shift RegisterMode Test Conditions

(VCC = 5.0 V20%; Load Capacitance = 80 pF)

符号

参数

12 MHz Osc

VariableOscillator

Units

Min

Max

Min

Max

TXLXL

Serial Port Clock Cycle Time期

1.0

12TCLCL

TQVXH

Output Data Setup to Clock Rising Edge

700

10TCLCL-133

TXHQX

Output Data Hold After Clock Rising Edge

2TCLCL-117

TXHDX

Input Data Hold After Clock Rising Edge

TXHDV

Clock Rising Edge to Input Data Valid

700

10TCLCL-133

ShiftRegister Mode Timing Waveforms

AC TestingInput/Output Waveforms(1)

Note: 1. ACInputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for alogic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max.for a logic 0.

FloatWaveforms(1)

Note: 1. Fortiming purposes, a port pin is no longer floating when a 100 mV change fromload voltage occurs. A port pin begins to float when 100 mV change from theloaded VOH/VOL level occurs.

OrderingInformation

Speed(MHz)

PowerSupply

Ordering Code

Package

Operation Range

5V+20%

AT89C51-12AC

AT89C51-12JC

AT89C51-12PC

AT89C51-12QC

44A

44J

40P6

44Q

Commercial

(0C to 70C)

AT89C51-12AI

AT89C51-12JI

AT89C51-12PI

AT89C51-12QI

44A

44J

40P6

44Q

Industrial

(-40C to 85C)

5V +20%

AT89C51-16AC

AT89C51-16JC AT89C51-16PC

AT89C51-16QC

44A

44J

40P6

44Q

Commercial

(0C to 70C)

AT89C51-16AI

AT89C51-16JI

AT89C51-16PI

AT89C51-16QI

44A

44J

40P6

44Q

Industrial

(-40C to 85C)

5V +20%

AT89C51-20AC

AT89C51-20JC AT89C51-20PC

AT89C51-20QC

44A

44J

40P6

44Q

Commercial

(0C to 70C)

AT89C51-20AI AT89C51-20JI AT89C51-20PI

AT89C51-20QI

44A

44J

40P6

44Q

Industrial

(-40C to 85C)

5V +20%

AT89C51-24AC

AT89C51-24JC AT89C51-24PC

AT89C51-24QC

44A

44J

40P6

44Q

Commercial

(0C to 70C)

AT89C51-24AI AT89C51-24JI AT89C51-24PI

AT89C51-24QI

44A

44J

40P6

44Q

Industrial

(-40C to 85C)

Package Type

44A

44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)

44J

44 Lead, Plastic J-Leaded Chip Carrier (PLCC)

40P6

40 Lead, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44Q

44 Lead, Plastic Gull Wing Quad Flatpack (PQFP)

P89C51Special Function Registers

SYMBOL

DESCRIPTION

BYTES

ADDRESS

BIT ADDRESS, SYMBOL

ACC

Accumulator

E0H

E7 E6 E5 E4 E3 E2 E1 E0

ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0

B register

F0H

F7 F6 F5 F4 F3 F2 F1 F0

B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0

DPH

Data Pointer High

83H

DPL

Data Pointer Low

82H

Interrupt Enable

A8H

AF –- –- AC AB AA A9 A8

EA ES ET1 EX1 ET0 EX0

IP*

Interrupt Priority

B8H

–- –- –- BC BB BA B9 B8

–- –- –- PS PT1 PX1 PT0 PX0

P0*

Port 0

80H

87 86 85 84 83 82 81 80

P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0

P1*

Port 1

90H

97 96 95 94 93 92 91 90 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0

P2*

Port 2

A0H

A7 A6 A5 A4 A3 A2 A1 A0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0

P3*

Port 3

B0H

B7 B6 B5 B4 B3 B2 B1 B0 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0

PCON

Power Control

87H

8D –- –- –- –- –- –- –- SMOD

PSW*

Program Status Word

D0H

D7 D6 D5 D4 D3 D2 D1 D0

CY AC F0 RS1 RS0 OV –- P

SBUF

Serial Data Buffer

99H

SCON*

Serial Control

98H

9F 9E 9D 9C 9B 9A 99 98

SM0 SM1 SM2 REN TB8 RB8 TI RI

Stack Pointer

81H

TCON*

Timer Control

Control

88H

8F 8E 8D 8C 8B 8A 89 88

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

TH0

Timer High 0

8CH

TH1

Timer High 1

8DH

TL0

Timer Low 0

8AH

TL1

Timer Low 1

8BH

TMOD

Timer Mode

89H

GATE C/^T M1 M0 GATE C/^T M1 M0

* SFRs arebit addressable.

– Reservedbits.

. Reset valuedepends on reset source.

描述

AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes的快速可擦写的只读程序存储器（PEROM）和128 bytes　的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flish存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。

主要性能参数：

与MCS-51产品指令系统完全兼容

4K字节可重复写flash闪速存储器

1000次擦写周期

全静态操作：0HZ－24MHZ

三级加密程序存储器

128*8字节内部RAM

32个可编程I/O口

2个16位定时／计数器

6个中断源

可编程串行UART通道

低功耗空闲和掉电模式

功能特性概述

　AT89C51提供以下标准功能：4K 字节flish闪速存储器，128字节内部RAM，32个I/O口线，两个16位定时／计数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89C51可降至0HZ的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许RAM，定时／计数器，串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位。

方框图

引脚功能说明

Vcc：电源电压

GND：地

P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复位口。作为输出口用时，每位能吸收电流的方式驱动8个逻辑门电路，对端口写“1”可作为高阻抗输入端用。

在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8位）和数据总线复用，在访问期间激活内部上拉电阻。

P1口：P1是一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可做熟出口。做输出口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（Iil）.

Flash编程和程序校验期间，P1接受低8位地址。

P2口：P2是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部地山拉电阻把端口拉到高电平，此时可作为输出口，作输出口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（Iil）。

在访问外部程序存储器获16位地址的外部数据存储器（例如执行 MOVX @DPTR指令）时，P2口送出高8位地址数据。在访问8位地址的外部数据存储器（如执行 MOVX @RI指令）时，P2口线上的内容（也即特殊功能寄存器（SFR）区中R2寄存器的内容），在整个访问期间不改变。

Flash编程或校验时，P2亦接受高地址和其它控制信号。

P3口：P3口是一组带有内部上拉电阻的8位双向I/O口。P3口输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对P3口写入“1”时，他们被内部上拉电阻拉高并可作为输出口。做输出端时，被外部拉低的P3口将用上拉电阻输出电流（Iil）。P3口除了作为一般的I/O口线外，更重要的用途是它的第二功能，如下表所示：

端口引脚

第二功能

P3.0

rxd (串行输入口)

P3.1

txd (串行输出口)

P3.2

^int0 (外中断0)

P3.3

^int1 (外中断1)

P3.4

t0 (定时/计数器0)

P3.5

t1 (定时/计数器1)

P3.6

^WR (外部数据存储器写选通)

P3.7

^RD (外部数据存储器读选通)

P3口还接收一些用于flash闪速存储器编程和程序校验的控制信号。

RST：复位输入。当振荡器工作时，RST引脚出现两个机器周期以上高电平将使单片机复位。

ALE/PROG：当访问外部程序存储器或数据存储器时，ALE（地址所存允许）输出脉冲用于所存地址的低8位字节。即使不访问外部存储器，ALE仍以时钟振荡频率的1/6输出固定的正脉冲信号，因此它可对外输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个ALE脉冲。

对flash存储器编程期间，该引脚还用于输入编程脉冲（^PROG）。

如有不要，可通过对特殊功能寄存器（SFR）区中的8EH单元的D0位置位，可禁止ALE操作。该外置位后，只要一条MOVX和MOVC指令ALE才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE无效。

^PSEN：程序存储允许（^PSEN）输出是外部程序存储器的读选通信号，当AT89C51由外部程序存储器取指令（或数据）时，每个机器周期两个^PSEN有效，即输出两个脉冲。在此期间，当访问外部数据存储器，这两次有效的^PSEN信号不出现。

EA/VPP:外部访问允许。欲使CPU仅访问外部程序存储器（地址为0000H---FFFFH），EA端必须保持低电平（接地）。需注意的是; 如果加密位LB1被编程，复位时内部会锁存EA端状态。

如 EA端为高电平（接VCC端），CPU则执行内部程序存储器中的指令。

Flash存储器编程时，该引脚加上+12V的编程允许电源VPP，当然这必须是该器件是使用12V编程电压VPP.

XTAL1:振荡器反相放大器的及内部时钟发生器的输出端。

XTAL2:振荡器反相放大器的输出端。

时钟振荡器：

AT89C51中有一个用于构成内部振荡器的高增益反相放大器，引脚XTAL1和XTAL2分别是该放大器的输入端和输出端。这个放大器与作为反馈的片外石英晶体或陶瓷谐振器一起构成自激振荡器，振荡电路参见图5。

外接石英晶体（或陶瓷谐振器）及电容C1、C2接在放大器的反馈回路中构成并联振荡电路。对外接电容C1、C2虽然没有十分严格的要求，但电容容量的大小会轻微影响振荡频率的高低、振荡器的稳定性、起振的难易程度及温度稳定性，如果使用石英晶体，我们推荐电容使用30PF+10PF，而如使用陶瓷谐振器建议选择40PF+10PF。

用户也可以采用外部时钟。采用外部时钟的电路如图5右所示。这种情况下，外部时钟脉冲接到XTAL1端，即内部时钟发生器的输入端，XTAL2则悬空

由于外部时钟信号是通过一个2分频触发器后作为内部时钟信号的，所以对外部时钟信号的占空比没有特殊要求，但最小高电平持续时间和最大的低电平持续时间应符合产品技术要求。

空闲模式

在空闲工作模式状态，CPU保持睡眠状态而所有片内的外设仍保持激活状态，这种方式由软件产生。此时，片内RAM和所有特殊功能寄存器的内容保持不变。空闲模式可由任何允许的中断请求或硬件复位终止。

终止空闲工作模式的方法有两种，其一是任何一条被允许中断的事件被激活，即可终止空闲工作模式。程序会首先响应中断，进入中断服务程序，执行完中断服务程序并仅随终端返回指令，下一条要执行的指令就是使单片机进入空闲模式那条指令后面的一条指令。其二是通过硬件复位也可将空闲工作模式终止，需要注意的是，当由硬件复位来终止空闲模式时，CPU通常是从激活空闲模式那条指令的下一条指令开始继续执行程序的，要完成内部复位操作，硬件复位脉冲要保持两个机器周期（24个时钟周期）有效，在这种情况下，内部禁止CPU访问片内RAM，而允许访问其它端口。为了避免可能对端口产生以外写入，激活空闲模式的那条指令后一条指令不应该是一条对端口或外部存储器的写入指令。

空闲和掉电模式外部引脚状态

模式

程序存储器

ALE

^PSEN

PORT0

PORT1

PORT2

PORT3

空闲模式

内部

数据

空闲模式

外部

浮空

数据

掉电模式

内部

数据

掉电模式

外部

浮空

数据

掉电模式

在掉电模式下，震荡器停止工作，进入掉电模式的指令是最后一条被执行的指令，片内RAM和特殊功能寄存器的内容在终止掉电模式前被冻结。退出掉电模式的唯一方法是硬件复位，复位后将重新定义全部特殊功能寄存器但不改变RAM中的内容，在VCC恢复到正常工作电平前，复位应无效，且必须保持一定时间以使振荡器重启动并稳定工作。

程序存储器的加密 ：AT89C51可使用对芯片上的3个加密位进行编程（P）或不编程（U）来得到如下表所示的功能：

加密位保护功能表

程序加密位

保护类型

LB1

LB2

LB3

没有程序保护功能

禁止从外部程序存储器中执行MOVC指令读取内部程序存储器的内容

除上表功能外，还禁止程序校验

除以上功能外，同时禁止外部执行

当加密位LB1被编程时，在复位期间，EA端的逻辑电平被采样并锁存，如果单片机上电后一直没有复位，则锁存起的初始值是一个随机数，且这个随机数会一直保持到真正复位为止。为使单片机能正常工作，被锁存的EA电平值必须与该引脚当前的逻辑电平一致。此外，加密位只能通过整片擦除的方法清除。

FLASH闪速存储器的编程：

AT89C51单片机内部有4K字节的FLASH PEROM,这个FLASH存储阵列出厂时已处于擦除状态（即所有存储单元的内容均为FFH），用户随时可对其进行编程。编程接口可接收高电平（+12V）或低电平（VCC）的允许编程信号，低电平编程模式适合于用户再线编程系统，而高电平编程模式可与通用EPROM编程器兼容。

AT89C51单片机中，有些属于低电压编程方式，而有些则是高电平编程方式，用户可从芯片上的型号和读取芯片内的签名字节获得该信息，见下表。

Vpp=12v

Vpp=5v

芯片顶面标识

AT89C51

xxxx

yyww

AT89C51

xxxx-5

yyww

签名字节

(030H)=1EH

(031H)=51H

(032H)=FFH

(030H)=1EH

(031H)=51H

(032H)=05H

AT89C51的程序存储器阵列是采用字节写入方式编程的，每次写入一个字节，要对整个芯片内的PEROM程序存储器写入一个非空字节，必须使用片擦除的方式将整个存储器的内容清除。

编程方法：

编程前，需按表1、图3和图4所示设置好地址，数据及控制信号， AT89C51编程方法如下：

1．在地址线上加上要编程单元的地址信号。

2．在数据线上加上要写入的数据字节。

3．激活相应的控制信号。

4．在高电压编程方式时，将^EA/VPP端加上+12V编程电压。

5．每对FLASH存储阵列写入一个字节或每写入一个程序加密位，加上一个ALE/^PROG编程脉冲，改变编程单元的地址和写入的数据，重复1—5步骤，直到全部文件编程结束。每个字节写入周期是自身定时地，通常约为1.5ms。

数据查询：AT89C51单片机用数据查询方式来检测一个写周期是否结束，在一个写周期中，如需要读取最后写入的那个字节，则读出的数据的最高位（P0.7）是原来写入字节最高位的反码。写周期完成后，有效的数据就会出现在所有输出端上，此时，可进入下一个字节的写周期，写周期开始后，可在任意时刻进行数据查询。

READY/^BUSY：字节编程的进度可通过“RDY/^BSY”输出信号监测，编程期间，ALE变为高电平“H”后P3.4(RDY/^BSY)端电平被拉低，表示正在编程状态（忙状态）。编程完成后，P3.4变为高电平表示准备就绪状态。

程序校验：如果加密位LB1、LB2没有进行编程，则代码数据可通过地址和数据线读回原编写的数据。加密位不可能直接变化。证实加密位的完成通过观察它们的特点和能力。

芯片擦除：利用控制信号的正确组合（表1）并保持ALE/^PROG引脚10ms的低电平脉冲宽度即可将PEROM阵列（4k字节）整片擦除，代码阵列在擦除操作中将任何非空单元写入“1”，这步骤需要再编程之前进行。

读片内签名字节：AT89C51单片机内有3个签名字节，地址为030H、031H和032H。用于声明该器件的厂商、型号和编程电压。读签名字节的过程和单元030H、031H和032H的正常校验相仿，只需将P3.6和P3.7保持低电平，返回值意义如下：

（030H）=1EH声明产品由ATMEL公司制造。

（031H）=51H声明为AT89C51单片机。

（032H）=FFH声明为12V编程电压。

（032H）=05H声明为5V编程电压。

编程接口：采用控制信号的正确组合可对FLASH闪速存储阵列中的每一代码字节进行写入和存储器的整片擦除，写操作周期是自身定时的，初始化后它将自动定时到操作完成。

表 1 FLASH存储器编程真值表

方式

RST

^PSEN

ALE/^PROG

^EA/Vpp

P2.6

P2.7

P3.6

P3.7

携代码数据

H/12V

读代码数据

写加密位

Bit-1

H/12V

Bit-2

H/12V

Bit-3

H/12V

片擦除

H/12V

读签名字节

注：片擦除操作时要求^PSEN脉冲宽度为10ms

FLASH编程和校验特性

TA = 0°C to 70°C, VCC = 5.0 10%

符号

参数

最小值

最大值

单位

Vpp⑴

编程电压

11.5

12.5

Ipp⑴

编程电流

1.0

1/Tclcl

时钟频率

MHZ

Tavgl

建立地址到^PSEN变低

48Tclcl

Tghax

^PSEN变低后地址保持不变

48Tclcl

Tdvgl

建立数据到 ^PSEN变低

48Tclcl

Tghdx

^PSEN变低吼数据保持不变

48Tclcl

Tehsh

P2.7(^enable)变高到Vpp

48Tclcl

Tshgl

加Vpp 到^PSEN 变低

Tghsl⑴

^PSEN后保持Vpp

Tglgh

^PSEN宽度

110

Tavqv

地址到数据有效

48Tclcl

Telqv

^enable低到数据有效

48Tclcl

Tehqz

^enable后数据浮空

48Tclcl

Tghbl

^PSEN变高到 ^busy变低

1.0

Twc

字节写周期

2.0

注：仅用于12V编程模式

Flash 编程和校验的波形时序（高电压编程方式 Vpp=12V）

Flash 编程和校验的波形时序（高电压编程方式Vpp=5V）

AT89C51的极限参数：

极限参数

操作温度 ...............................-55°C to +125°C

储藏温度 .................................-65°C to +150°C

任意引脚对地电压 ..............................-1.0V to +7.0V

最高工作电压 ...........................6.6V

支流输出电流 ................................... 15.0 mA

直流特性

符号

参数

条件

最小值

最大值

单位

Vil

输入低电压

(except ^EA)

-0.5

0.2Vcc-0.1

Vil1

输入低电压(^EA)

-0.5

0.2Vcc-0.3

Vih

I输入高电压

Except XTAL1,XTAL2

0.2Vcc+0.9

Vcc+0.5

Vih1

输入高电压

(XTAL1,RST)

0.7Vcc

Vcc+0.5

Vol

输出低电压⑴(ports 1,2,3 )

Iol=1.6mA

0.45

Vol1

输出低电压⑴(port0,ALE,^PSEN)

Ioh=3.2mA

0.45

Ioh=-60uA,Vcc=-5V+10%

2.4

Ioh=-25uA

0.75Vcc

Voh

输出高电压⑴(ports 1,2,3 )

Ioh=-60uA,Vcc=5V+10%

0.9Vcc

Voh1

输出高电压⑴(port0,ALE,^PSEN)

Ioh=-800UA,Vcc=5V+10%

2.4

Ioh=-300uA,

0.75Vcc

Ioh=-80uA

0.9Vcc

Iil

逻辑0输入电流(ports 1,2,3)

Vin=0.45V

-50

Itl

逻辑1到0转换电流(ports 1,2,3)

Vin=2V,Vcc=5V+10%

-650

Ili

输入漏电流(port 0, ^EA)

0.45<Vin<Vcc

+10

RRWR

复位下拉电阻

300

kom

Cio

引脚电容

Test freq=1MHZ,TA=25℃

Icc

消耗电流

Active mode, 12MHZ

Idle mode,12MHZ

掉电模式消耗电流⑵

Vcc=6V

100

Vcc=3V

注意：1 在在稳态(非瞬态)条件下，IOL对外有极限如下：

每个引脚输出的最大IOL为10 mA

P口输出的最大IOL：Port 0: 26 mA

Ports 1, 2, 3: 15 mA

对于所有的输出引脚的最大总IOL为71 mA

2 掉电模式的最小电压是2V

交流特性

在以下条件下，P0口，ALE/^PROG,^PSEN的负载电容为100pF，其它输出口负载电容为80Pf.

外部程序数据存储器特性

符号

参数

12 MHz 时钟振荡器

16 to 24 MHz 时钟振荡器

Units

Min

Max

Min

Max

1/TCLCL

时钟频率

MHz

TLHLL

ALE 脉冲宽度

127

2TCLCL-40

TAVLL

地址有效到ALE变低时间

TCLCL-13

TLLAX

ALE 变低后，地址保持时间

TCLCL-20

TLLIV

ALE 变低到指令输入有效

233

4TCLCL-65

TLLPL

ALE 变低到 PSEN 变低时间

TCLCL-13

TPLPH

PSEN脉冲宽度

205

3TCLCL-20

TPLIV

PSEN变低到指令输入有效

145

3TCLCL-45

TPXIX

PSEN建立后指令保持时间

TPXIZ

PSEN建立后指令浮空时间

TCLCL-10

Tpxav

PSEN 建立后到地址有效时间

TCLCL-8

TAVIV

建立地址道指令输入有效

312

5TCLCL-55

TPLAZ

PSEN变低到地址浮空时间

TRLRH

RD 脉冲宽度

400

6TCLCL-100

TWLWH

WR 脉冲宽度

400

6TCLCL-100

TRLDV

RD变低到数据输入有效时间

252

5TCLCL-90

TRHDX

RD建立后数据保持时间

TRHDZ

RD建立后数据浮空时间

2TCLCL-28

TLLDV

ALE变低到数据输入有效时间

517

8TCLCL-150

TAVDV

地址建立到数据输入有效时间

585

9TCLCL-165

TLLWL

ALE 变低到RD或WR 变低时间

200

3TCLCL-50

3TCLCL+50

TAVWL

地址建立到RD或WR变低时间

203

4TCLCL-75

TQVWX

数据有效到WR转换时间

TCLCL-20

TQVWH

数据有效到WR变高时间

433

7TCLCL-120

TWHQX

WR建立到数据保持时间

TCLCL-20

TRLAZ

RD 变低到地址浮空时间

TWHLH

RD 或WR变高到ALE 变高时间

123

TCLCL-20

TCLCL+25

外部程序存储器读周期

外部数据存储器读周期

外部数据存储器写周期

外部时钟驱动波形

外部时钟驱动特性

符号

参数

最小值

最大值

单位

1/TCLCL

时钟震荡频率

MHz

TCLCL

时钟周期

41.6

TCHCX

高电压时间

TCLCX

低电压时间

TCLCH

上升时间

TCHCL

下降时间

串行口时序: 移位寄存器测试条件

(VCC = 5.0 V 20%; 浮在容抗 = 80pF)

符号

参数

12 MHz Osc

VariableOscillator

Units

Min

Max

Min

Max

TXLXL

串行口时钟周期

1.0

12tCLCL

TQVXH

建立数据输出到始终上升沿

700

10tCLCL-133

TXHQX

时钟上升沿建立后输出数据保持时间

2tCLCL-117

TXHDX

时钟上升沿建立后输入数据保持时间

TXHDV

时钟上升沿建立到输入数据下降

700

10tCLCL-133

移位寄存器时序波形

AC 测试输入/输出波形(1)

注意：输入的交流电压能够驱动的测试是 VCC - 0.5V 为逻辑1， 0.45V 为逻辑 0.定时测量VIH的最小值为逻辑1和 VIL 的最大值为逻辑0.

浮空波形(1)

注意：定时目的，当装载电压发生源有100mV电压变化时，某个P口引脚不悬空，当装载VOH/VOL的有100mV电压变化时，P口引脚悬空。

信息标准

Speed(MHz)

Power Supply

Ordering Code

Package

Operation Range

5V +20%

AT89C51-12AC

AT89C51-12JC

AT89C51-12PC

AT89C51-12QC

44A

44J

40P6

44Q

Commercial

(0C to 70C)

AT89C51-12AI

AT89C51-12JI

AT89C51-12PI

AT89C51-12QI

44A

44J

40P6

44Q

Industrial

(-40C to 85C)

5V +20%

AT89C51-16AC

AT89C51-16JC AT89C51-16PC

AT89C51-16QC

44A

44J

40P6

44Q

Commercial

(0C to 70C)

AT89C51-16AI

AT89C51-16JI AT89C51-16PI

AT89C51-16QI

44A

44J

40P6

44Q

Industrial

(-40C to 85C)

5V +20%

AT89C51-20AC

AT89C51-20JC AT89C51-20PC

AT89C51-20QC

44A

44J

40P6

44Q

Commercial

(0C to 70C)

AT89C51-20AI AT89C51-20JI AT89C51-20PI

AT89C51-20QI

44A

44J

40P6

44Q

Industrial

(-40C to 85C)

5V +20%

AT89C51-24AC

AT89C51-24JC AT89C51-24PC

AT89C51-24QC

44A

44J

40P6

44Q

Commercial

(0C to 70C)

AT89C51-24AI AT89C51-24JI AT89C51-24PI

AT89C51-24QI

44A

44J

40P6

44Q

Industrial

(-40C to 85C)

封装类型

44A

44 脚， TQFP封装

44J

44 脚, PLCC封装

40P6

40 脚, 双列直插PDIP封装

44Q

44 脚, PQFP封装

P89C51 特殊功能寄存器

符号

说明

字节地址

位地址 /位符号

ACC*

累加器

E0H

E7 E6 E5 E4 E3 E2 E1 E0

ACC.7ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0

B 寄存器

F0H

F7 F6 F5 F4 F3 F2 F1 F0

B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0

DPH

数据指针高字节

83H

DPL

数据指针低字节

82H

IE*

中断优先

A8H

AF - - AC AB AA A9 A8

EA ES ET1 EX1 ET0 EX0

IP*

中断优先级

B8H

- - - BC BB BA B9 B8

- - - PS PT1 PX1 PT0 PX0

P0*

I/O口 0

80H

87 86 85 84 83 82 81 80

P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0

P1*

I/O口 1

90H

97 96 95 94 93 92 91 90

P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0

P2*

I/O口2

A0H

A7 A6 A5 A4 A3 A2 A1 A0

P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0

P3*

I/O口 3

B0H

B7 B6 B5 B4 B3 B2 B1 B0

P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0

PCON

电源控制

87H

8D - - - - – - -

SMOD

PSW*

程序状态字

D0H

D7 D6 D5 D4 D3 D2 D1 D0

CY AC F0 RS1 RS0 OV –- P

SBUF

串行数据缓冲器

99H

SCON*

穿行后控制

98H

9F 9E 9D 9C 9B 9A 99 98

SM0 SM1 SM2 REN TB8 RB8 TI RI

堆栈指针

81H

TCON*

定时器控制

88H

8F 8E 8D 8C 8B 8A 89 88

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

TH0

定时器0高字节

8CH

TH1

定时器1高字节

8DH

TL0

定时器0低字节

8AH

TL1

定时器1低字节

8BH

TMOD

定时器模式

89H

GATE C/^T M1 M0 GATE C/^T M1 M0

注：带“*”号的SFR 可位寻址。

“－”表示保留位

复位值由复位源确定。