EDA洗衣机控制器

1. 时序仿真图

2。减计数器

 

 

 

3．数码管显示

 

4．设置时间

 

 

5．译码输出

顶层文件

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity total is

port(

              clk1,start1,load1:in std_logic;

              k1:in std_logic_vector(9 downto 0);

              REV1,RUN1,PAUSE1:out std_logic;

              h,i,j,k,l,m,n,o,p,q,r,s,t,u:out std_logic

       -- time_is_end:out std_logic

    );

end entity total;

architecture one of total is

component counter --计数器

  port(clk,start:in std_logic;

     k:in STD_LOGIC_VECTOR(7 downto 0);

     time_remain:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);

     time_is_up:out std_logic

);

end component;

 

component decoder--译码器

  port( Q1,Q2: in std_logic;

       REV,RUN,PAUSE: out std_logic );

end component;

 

component settime --设置时间

 port(load:in std_logic;

k:in std_logic_vector(9 downto 0);

o:out std_logic_vector(7 downto 0)

);

end component;

 

component shixu --时序

 port(cp,en,rd:in std_logic;

       q1,q2:out std_logic--00为停机，10为正转，01为反转

);

end component;

 

component showtime--显示时间

 port(remain_time:in std_logic_vector(7 downto 0);

 

a,b,c,d,e,f,g,a1,b1,c1,d1,e1,f1,g1:out std_logic);

end component;

signal o1:std_logic_vector(7 downto 0);--设置的输出信号

signal remain:std_logic_vector(7 downto 0);

signal voice,n1,n2:std_logic;

begin

u1:settime port map(load=>load1,k=>k1,o=>o1);--设置时间部分

u2:counter port map(clk=>clk1,start=>start1,o1=>k1,time_remain=>remain,time_is_up=>voice);--计数器部分

u3:shixu port map(cp=>clk1,en=>start1,rd=>voice,q1=>n1,q2=>n2);--时序部分

u4:decoder port map(n1=>Q1,n2=>Q2,REV=>REV1,RUN=>RUN1,PAUSE=>PAUSE1);--译码部分

u5:showtime port map(remain_time=>remain,a1=>h,b1=>i,c1=>j,d1=>k,e1=>l,f1=>m,g1=>n,a=>o,b=>p,c=>q,d=>r,e=>s,f=>t,g=>u);--显示部分

end architecture one;

2.减计数器部分

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity counter is

 port(clk,start:in std_logic;

     k:in STD_LOGIC_VECTOR(7 downto 0);

     time_remain:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);

     time_is_up:out std_logic

);

end counter;

architecture rtl of counter is

begin

process(clk)

variable time_second:std_logic_vector(5 downto 0);

   begin

     if(clk'event and clk='1')

      then if(start='0')

      then time_remain<=k;--初始化接受到预制的数值

       time_second:="111011";--秒60

         else if(time_second=0)--当秒走完时

              then if(time_remain(3 downto 0)>0)--低四位

                   then time_remain(3 downto 0)<=time_remain(3 downto 0)-1;--减记数

                        time_second:="111011";  

                   else if(time_remain(7 downto 4)>0)--低四位向高位借位

                        then time_remain(7 downto 4)<=time_remain(7 downto 4)-1;

                        time_remain(3 downto 0)<="1001";

                        time_second:="111011"; 

                       end if;

                   end if;

            else --当秒60没有走完时

                              time_second:=time_second-1;--秒表计数的实现

                 end if;

                  if(time_remain=0)--时间是否结束的判定

                  then time_is_up<='0';

                  else time_is_up<='1';

                  end if;

            end if;     

         end if;

 end process;

end rtl;

 

3。译码部分

library ieee;

use ieee.std_logic_1164.all;

entity decoder is

   port( Q1,Q2: in std_logic;

       REV,RUN,PAUSE: out std_logic );

end decoder;

architecture rtl of decoder is

signal choose:std_logic_vector(1 downto 0);

begin

choose(1)<=q1;choose(0)<=q2;

process(choose)

begin

case choose is

when "00"=>REV<='0';RUN<='0';PAUSE<='1';

when "10"=>REV<='0';RUN<='1';PAUSE<='0';

when "01"=>REV<='1';RUN<='0';PAUSE<='0';

when others=>REV<='0';RUN<='0';PAUSE<='0';

end case;

end process;

end rtl;

4。设置时间

Library ieee;

Use ieee.std_logic_1164.all;

Use ieee.std_logic_unsigned.all;

Entity settime is

port(load:in std_logic;

k:in std_logic_vector(9 downto 0);

o:out std_logic_vector(7 downto 0)

);

end settime;

architecture rtl of settime is

signal ee:std_logic_vector(7 downto 0);

begin

process (load)

begin

if (load'event and load='1')

then

case k is

when "1000000000"=>ee<="00000001";

when "0100000000"=>ee<="00000010";

when "0010000000"=>ee<="00000011";

when "0001000000"=>ee<="00000100";

when "0000100000"=>ee<="00000101";

when "0000010000"=>ee<="00000110";

when "0000001000"=>ee<="00000111";

when "0000000100"=>ee<="00001000";

when "0000000010"=>ee<="00001001";

when "0000000001"=>ee<="00010000";

when others=>ee<="00000000";

end case;

end if;

end process;

o<=ee;

end rtl;

5.时序

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity shixu is

 port(cp,en,rd:in std_logic;

       q1,q2:out std_logic--00为停机，10为正转，01为反转

);

end shixu;

architecture rtl of shixu is

begin

process(cp)

variable  state:std_logic; --0代表正转，1代表反转

variable wash_time:std_logic_vector(4 downto 0);

variable wait_time:std_logic_vector(3 downto 0);

begin

if(cp'event and cp='1')

then if(rd='1')then if(en='0')then

wash_time:="10011";wait_time:="1001";

Q1<='0';Q2<='0';--停机状态

else if(wash_time>0)

               then wash_time:=wash_time-1;

                    wait_time:="1001";--等待时间恢复

                            --Q1<='1';Q2<='0';--正转

               else if(wait_time>0)--运行时间结束，等待时间未到

                    then  wait_time:=wait_time-1; --等待时间减1

                    else wash_time:="10011"; --等待时间结束，继续运行

                                           wait_time:="1001";

                         state:=not state;                     

                    end if;

               end if;

   --   end if; 将译码也加入同步时序，可以减少毛刺                        

                if(wash_time=0)

               then Q1<='0';Q2<='0';--暂停

               else if(state='0')--正转

                   then  Q1<='1';Q2<='0';

                   else Q1<='0';Q2<='1';--反转

                   end if;

                end if;

          --else Q1<='0';Q2<='0';--暂停

          end if;

        end if;

end if;

 end process;

end rtl;

 6。显示时间

Library ieee;

Use ieee.std_logic_1164.all;

Use ieee.std_logic_unsigned.all;

entity showtime is

port(remain_time:in std_logic_vector(7 downto 0);

 

a,b,c,d,e,f,g,a1,b1,c1,d1,e1,f1,g1:out std_logic);

end showtime;

architecture rtl of showtime is

 

signal temp:std_logic_vector(6 downto 0);

signal temp1:std_logic_vector(6 downto 0);

signal bcd:std_logic_vector(3 downto 0);

signal bcd1:std_logic_vector(3 downto 0);

 

begin

 

 

 

bcd<=remain_time(7 downto 4);

 

bcd1<=remain_time(3 downto 0);

 

process (bcd)

begin

case bcd is

when  "0000"=>temp<="0000001";

when  "0001"=>temp<="1001111";

when  "0010"=>temp<="0010010";

when  "0011"=>temp<="0000110";

when  "0100"=>temp<="1001100";

when  "0101"=>temp<="0100100";

when  "0110"=>temp<="0100000";

when  "0111"=>temp<="0001111";

when  "1001"=>temp<="0000100";

when  others=>temp<="0000100";

end case;

a<=temp(6);b<=temp(5);c<=temp(4);d<=temp(3);e<=temp(2);f<=temp(1);g<=temp(0);

end process;

process (bcd1)

begin

case bcd1 is

when  "0000"=>temp1<="0000001";

when  "0001"=>temp1<="1001111";

when  "0010"=>temp1<="0010010";

when  "0011"=>temp1<="0000110";

when  "0100"=>temp1<="1001100";

when  "0101"=>temp1<="0100100";

when  "0110"=>temp1<="0100000";

when  "0111"=>temp1<="0001111";

when  "1001"=>temp1<="0000100";

when  others=>temp1<="0000100";

end case;

a1<=temp1(6);b1<=temp1(5);c1<=temp1(4);d1<=temp1(3);e1<=temp1(2);f1<=temp1(1);g1<=temp1(0);

end process;

end rtl;