sharc21479 uart总结

Register Overview

 Line Control Register (UARTxLCR). Controls the format of the data character frames. It selects word length, number of stop bits and parity.

在UARTxLCR中的第七位UARTDLAB

Divisor Latch Access Bit. Because some IOP registers share the same address, this bit provides access as follows.
0 = Enable access to UART0THR, UART0RBR, and UART_IER registers
1 = Enable access to UART0DLL and UARTxDLH registers

因为“Some UART registers share the same IOP address. The UART0DLL registers are mapped to the same address as the UARTxTHR and UART0RBR registers. The UART0DLH registers are mapped to the same address as the interrupt enable registers (UART0IER).

Divisor Latch High/Low Register (UARTxDLL/UARTxDLH). Characterize the UART bit rate. The divisor is split into the divisor latch low byte (UARTxDLL) and the divisor latch high byte (UARTxDLH).

The fundamental timing clock of the UART module is peripheral clock/16 (PCLK/16).

The bit rate is characterized by the peripheral clock (PCLK) and the 16-bit divisor. The divisor is split into the UART divisor latch low byte register (UARTDLL) and the UART divisor latch high byte register (UARTDLH). These registers form a 16-bit divisor.

The UART follows an asynchronous serial communication protocol with these options:
• 5 – 8 data bits
• 1 or 2 stop bits
• None, even, or odd parity
• Baud rate = PCLK/(16 × divisor), divisor value can be from 1 to 65,536

Transmit and receive channels are both buffered. The UARTTHR register buffers the transmit shift register (UARTTSR) and the UARTRBR register buffers the receive shift register (UARTRSR). The shift registers are not directly accessible by software.