启动代码之Option.inc

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;===========================================
; NAME: OPTION.A
; DESC:
Configuration options for .S files
; HISTORY:
; 02.28.2002: ver 0.0
;
03.11.2003: ver 0.0 attached for 2440.
; jan E, 2004: ver0.03 modified for
2440A01.
;===========================================
;这个Option.inc文件主要是为设置时钟服务的，选择好分频系数

;Start address of each stacks,
_STACK_BASEADDRESS EQU
0x33ff8000
_MMUTT_STARTADDRESS EQU 0x33ff8000
_ISR_STARTADDRESS EQU
0x33ffff00

GBLL USE_MAIN
;定义一个全局的逻辑变量，变初始化为FALSE
;USE_MAIN SETL {TRUE}
USE_MAIN SETL {FALSE}

GBLL PLL_ON_START ;定义一个全局的逻辑变量，变初始化为TRUE
PLL_ON_START SETL {TRUE}

GBLL ENDIAN_CHANGE ;定义一个全局的逻辑变量，变初始化为FALSE
ENDIAN_CHANGE SETL {FALSE}

GBLA ENTRY_BUS_WIDTH ;定义一个全局的数字变量，变初始化为16
ENTRY_BUS_WIDTH SETA 16

;BUSWIDTH = 16,32    ;定义一个全局的数字变量，变初始化为32
GBLA    BUSWIDTH ;max.
bus width for the GPIO configuration
BUSWIDTH SETA    32

GBLA UCLK ;定义一个全局的数字变量，变初始化为48000000
UCLK SETA 48000000

GBLA XTAL_SEL ;定义一个全局的数字变量，变初始化为12000000
GBLA FCLK ;定义一个全局的数字变量，变初始化为304000000
GBLA CPU_SEL ;定义一个全局的数字变量，变初始化为32440001

;(1) Select CPU
;CPU_SEL SETA 32440000 ; 32440000:2440X.
CPU_SEL
SETA 32440001 ; 32440001:2440A

;(2) Select XTaL
XTAL_SEL SETA 12000000
;XTAL_SEL SETA 16934400

;(3) Select
FCLK
FCLK SETA 304000000
;FCLK SETA 296352000

;(4) Select Clock
Division (Fclk:Hclk:Pclk)
CLKDIV_VAL EQU 7 ; 0=1:1:1, 1=1:1:2, 2=1:2:2,
3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.
;定义时钟比例

;--------------------------------------------
;下面根据外部晶振是12MMhz（else是16.9344Mhz),再根据我们的主时钟是（271.5MHz或304.8MHz），决定分频系数M_MDIV、M_PDIV、M_SDIV
;根据我们的USB时钟（48MHz或者96MHz），决定分频系数U_MDIV、U_PDIV、U_SDIV
;--------------------------------------------
[
XTAL_SEL = 12000000 ;[是IF伪操作的同义词，|是ELSE伪操作的同义词，]是ENDIF伪操作的同义词

[ FCLK =
271500000
M_MDIV EQU 173 ;Fin=12.0MHz
Fout=271.5MHz
M_PDIV EQU 2
[ CPU_SEL = 32440001
M_SDIV EQU 2 ;
2440A
|
M_SDIV EQU 1 ; 2440X
]
]

[ FCLK =
304000000
M_MDIV EQU 68 ;Fin=12.0MHz Fout=304.8MHz
M_PDIV EQU 1
[
CPU_SEL = 32440001
M_SDIV EQU 1 ; 2440A
|
M_SDIV EQU 0 ;
2440X
]
]

[ UCLK = 48000000
U_MDIV EQU 56 ;Fin=12.0MHz
Fout=48MHz
U_PDIV EQU 2
U_SDIV EQU 2
]
[ UCLK =
96000000
U_MDIV EQU 56 ;Fin=12.0MHz
Fout=96MHz
U_PDIV EQU 2
U_SDIV EQU 1

]

| ; else if XTAL_SEL = 16.9344Mhz

[ FCLK =
266716800
M_MDIV EQU 118 ;Fin=16.9344MHz
M_PDIV EQU 2
[ CPU_SEL =
32440001
M_SDIV EQU 2 ; 2440A
|
M_SDIV EQU 1 ;
2440X
]
]

[ FCLK =
296352000
M_MDIV EQU 97 ;Fin=16.9344MHz
M_PDIV EQU 1
[ CPU_SEL =
32440001
M_SDIV EQU 2 ; 2440A
|
M_SDIV EQU 1 ;
2440X
]
]
[ FCLK =
541900800
M_MDIV EQU 120 ;Fin=16.9344MHz
M_PDIV EQU 2
[ CPU_SEL =
32440001
M_SDIV EQU 1 ; 2440A
|
M_SDIV EQU 0 ;
2440X
]
]

[ UCLK = 48000000
U_MDIV EQU 60 ;Fin=16.9344MHz
Fout=48MHz
U_PDIV EQU 4
U_SDIV EQU 2
]
[ UCLK =
96000000
U_MDIV EQU 60 ;Fin=16.9344MHz
Fout=96MHz
U_PDIV EQU 4
U_SDIV EQU 1
]

] ; end of if
XTAL_SEL = 12000000.