ADSP-21369 sports碰到问题

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ADSP的音频串口提供的例子程序跑起来的时候碰到一个怪现象，24bit的音频数据，在数据缓冲区里面的自动存为右对齐，这样对处理是很有好处，但是在输出的时候发现原本左对齐的数据，前24bit是没有问题的，但是后8bit全部变为高电平了，虽然这样不影响输出的音频，但是对于AES的音频来说，这8bit应该是携带V,U等信息的，找了很长时间，没有找到想过的描述寄存器，不知道何解…………

Mode Selection
The serial port operating mode can be selected via the SPCTLx and the
SPMCTLx/y registers.
1. The operating mode bit 11 (OPMODE) of the SPCTLx register selects
between I2S, left-justified, and standard serial/multichannel mode.
13 FSR Reserved
14 IFS Reserved IMFS
15 DIFS Reserved
16 LFS L_FIRST LMFS
17 LAFS OPMODE Reserved
18 SDEN_A
19 SCHEN_A
20 SDEN_B
21 SCHEN_B
22 FS_BOTH Reserved
23 BHD
24 SPEN_B Reserved
25 SPTRAN
Status
26 DERR_B
27–28 DXS_B
29 DERR_A
30–31 DXS_A
Table 7-6. SPCTLx Control Bit Comparison (Cont’d)
Bit Standard Serial
Mode
I2S and Left-justified Mode
Packed Mode Multichannel Mode
ADSP-2137x SHARC Processor Hardware Reference 7-23 Serial Ports

2. The operating mode bit 17 (OPMODE) of the SPCTLx register selects
     between I2S mode and left-justified mode.
3. For packed mode, bit 11 (OPMODE) of the SPCTLx register and bit 0
   (MCEA) in the SPMCTLx register enables the A channels and bit 23
   (MCEB) in the SPMCTLx register enables the B channels.
4. In multichannel mode, the bit 0 (MCEA) in the SPMCTLx register
   enables the A channels and the bit 23 (MCEB) in the SPMCTLx register
   enables the B channels.
5. The OPMODE bit 17 serves for standard serial mode as late frame sync
   bit (LAFS).

看完之后，发现是不是可以把w-lenth配置为32bit就可以了，回去试试。