test
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library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity pTransfer is --定义实体名为pTransferport(clk_in:in std_logic;clk_out:buffer std_logic;c_out:out std_logic_vector(6 downto 0));end pTransfer;architecture para of pTransfer is --定义结构体名为parasignal freDivide:integer range 0 to 999999;signal signalString:integer range 0 to 14;signal clk,flag,q_out,q,cp_control,control,a,b,c,d:std_logic;signal tmp:std_logic_vector(7 downto 0);beginp1:process(clk_in) --分频器1MHz分为1Hzbeginif clk_in'event and clk_in='1' thenif freDivide=999999 thenfreDivide<=0;elsefreDivide<=freDivide+1;end if;if freDivide=500000 thenclk<='1';elseclk<='0';end if;end if;end process p1;clk_out<=clk;p2:process(clk) --函数信号发生器111100011011010beginif clk'event and clk='1' thenif signalString=14 thensignalString<=0;elsesignalString<=signalString+1;end if;end if;end process p2;p3:process(signalString)begincase signalString iswhen 4|5|6|8|9|12|14=>q_out<='0';when others=>q_out<='1';end case;end process p3;p4:process(clk) --串并转换 begin if clk'event and clk='1' thentmp(7)<=tmp(6);tmp(6)<=tmp(5);tmp(5)<=tmp(4);tmp(4)<=tmp(3);tmp(3)<=tmp(2);tmp(2)<=tmp(1);tmp(1)<=tmp(0);tmp(0)<=q_out;end if;end process;p5:process (tmp(0),tmp(1),tmp(2),tmp(3)) --并行检测beginif (tmp(0)='0') thena<='1';else a<='0';end if;if(tmp(1)='0') thenb<='1';else b<='0';end if;if(tmp(2)='0') thenc<='1';else c<='0';end if;if(tmp(3)='1') thend<='1';else d<='0';end if;end process;flag<=a and b and c and d;cp_control<=clk or q;p6:process --控制信号beginwait until cp_control='1'; q<=flag; end process;control<=q and clk; p7:process(control) --锁存器输出 begin if control'event and control='0' thenc_out(6)<=not tmp(7);c_out(5)<=not tmp(6);c_out(4)<=not tmp(5);c_out(3)<=not tmp(4);c_out(2)<=not tmp(3);c_out(1)<=not tmp(2);c_out(0)<=not tmp(1); end if; end process; end para;
