FPGA学习笔记6-Quartus II中的TCL脚本

Agenda
-TCL Scripting support in quartus II Software
-Creating Projects
-Compiling Designs
-Accessing Report Data
-Analyzing

TCL Scripting Benefits
-Custom Analysis
  Extract Only Report Information You Need
-Automation
  Eliminate Manual Steps in Graphical User Interface(GUI)
  Interface with Other Design Software
-Reproducibility
  Easier Project Maintenance and Documentation

Quartus II TCL Support
-Quartus II Software Provides Extensive Tcl Scripting Support
-Four Command-Line Executables Include Tcl Interpreter
-Quartus II Tcl API Include Over 150 Commands in 14 Packages

TCL Packages
-TCL Commands Grouped by Function in Packages
-Subset of Available Packages is Preloaded
  Reduces Memory Footprint
  Load Packages as Necessary In TCL Script
-Not All Packages Available in All Command-Line Executables
  Packages Align with Executable Functionality
  Timeing Analysis Package Only in quartus_tan

Commonly Used Packages

name  Description::quartus::projectCreate Projects,Make Assignments::quartus::flow Complie Projects,Run Common Flows::quartus::reportAccess Report Tables,Create Custom Reports::quartus::timing Compute and Report Timing Paths::quartus::timing_report  List Timing Paths

-Loading Packages
  load_package <name> [-version <version>]
      ::quartus:: in Name is Optional 
  Alternately Use TCL package require Command

::quartus::project Package
-Create Projects and Make Assignments
-Some Commonly Used Commands
  Project and Revision
      project_new,project_open,project_close,create_revision,set_current_revision
  General Assignment
      set_global_assignment,set_instance_assignment
  Specific Assignment

      set_location_assignment,set_input_delay,set_output_delay,

      set_multicycle_assignment,create_base_clock,timegroup

::quartus::project Example
-Create Project and Make Assignments
  Use fir_filter Tutorial Files
Example:
project_new fir_filter -revision filtref -overwrite
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C6F256C6
set_global_assignment -name BDF_FILE filtref.bdf
set_global_assignment -name TOP_LEVEL_ENTITY filtref
set_location_assignment -to clk Pin_G1
create_base_clock -fmax "100 MHZ" -target clk clocka
create_relative_clock -base_clock clocka -divede 2 \
       -offset "500 ps" -target clkx2 clockb
set_multicycle_assignment -from clk -to clkx2 2

project_close

Saving Assignments to QSF
-Assignments Not Automatically Saved to Quartus II setting File(QSF)
-Assignments Must Be Saved to QSF before Using Them
  Before a System Call,for Example
-Some Command Save Assignments Automatically
-project_close,execute_flow,execute_module
-Use export_assignments Command for Manual Control

export_assignments Scenario
-Commandly Used Before A System Call for Command-line Executable

Example:

project_open $project_name
set_global_assignments -name FAMILY Stratix
#Before calling quartus_map,save the FAMILY assignment
export_assignemnts
#Now call quartus_map
qexec "quartus_map $project_name"

-Using execute_moudle -tool map instead of qexec Saves Assignments Automatically

::quartus::flow Package
-Compile Projects and Run Common Flows
-Two Commands
  execute_flow <flow name>
      compile,-check_ios,etc
  execute_moudle -tool <tool>
      map,fit,tan,etc
-Package Is Not Loaded by Default
  Use load_package flow Before Either Command

::quartus::flow Example
-Open Project and Compile Design
  Bulids on Previous Example

Example:

load_package flow
project_open fir_filter -revision filtref
execute_flow -compile
project_close

-Could Add execute_flow -compile Command to Previous Example
  Create Project and Complie with One Script

Pop Quiz
-Write One Script that Creates and Compiles Project
-Combine Project Creation Script with Project Compilation Script

Pop Quiz Answer

load_package flow
project_new_filter -revision filtref -overwrite
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C6F256C6
set_global_assignment -name BDF_FILE filtref.bdf
set_global_assignment -name TOP_LEVEL_ENTITY filtref
set_location_assignment -to clk Pin_G1
create_base_clock -fmax "100 MHz" -target clk clocka
create_relative_clock -base_clock clocka -divide 2\
     -offset "500 ps" -target clkx2 clockb
set_multicycle_assignment -from clk -to clkx2 2
execute_flow -compile
project_close

::quartus::report Package
-Access Report Tables and Create Custom Report
-Some Commonly Used Commands
  Report Management
      load_report,unload_report,create_report_panel
  Information About Reports
  get_report_panel_names,get_number_of_rows
  Access Report Data
      get_report_panel_row,get_report_panel_data,get_timing_analysis_summary_result

Report Structure
-Commands to Access Report Data Require Panel Name
-Panel Name is the Hierarchical Path to the Panel
-Hierarchy Uses || Characters
  <Folder Name> || <Panel Name>
-Selected Report Panel Named "Timing Analyzer || Timing Analyzer Settings"
-First-Level Reports Have No ||
  Flow Log Panel Named Flow Log
-Panels Are Tabular
  Rows and Columns
-Refer to Rows and Columns by Number or Name
-Numbering Starts at Zero
-Row 0 Has Column Headings

Panel Structure Example
-row2 
-row_name "Timing Models"
-col1
-col_name Setting

Example:

get_report_panel_data -name "Timing Analyzer||Timing Analyzer Settings"\
   -row_name "Timing Models" -col_name Setting

::quartus::report Example
-Print Number of Failing Paths per Clock Domain
-Use Timing Analyzer Summary Panel
  Failed Paths Column
-Print Number of Failing Path Per Clock Domain

Example:

load_package report
project_open fit_filter -revision filtref
load_report
set panel_name "Timing Analyzer||Timing Analyzer Summary"
set num_panel_rows [get_number_of_rows -name $panel_name]
for {set i 1} {$ < $num_panel_rows} {incr i}{
  set summary_type [get_report_panel_data -name $panel_name \
   -row $i -col_name Type]
  if{[regexp {Clock Setup:(.*)}$summary_type match clk_name]}{
    set num_failed_paths [get_report_panel_data -name $panel_name \
      -row $i -col_name "Failed Paths"]
    puts "Clock domain $clk_name has $num_failed_paths failing paths"
  }
}
unload_report
project_close

Pop Quiz
-Print a Message Saying whether Project Meets Timing After Compilation
  Assume Project is open
  Hint:How many Paths Fail if Timing Is Met?

Pop Quiz Answer

#Assume project is open;don't forget to load the report load_report
if {0==[get_report_panel_data -name \
      {Timing Analyzer||Timing Analyzer Summary} \
       -row_name {Total number of failed paths} \
       -col_name {Failed Paths}]}{
       puts "Design meets timing"
}else{
    puts "Design does not meets timing"
}
unload_report

::quartus::timing Package
-Compute and Report Timing Paths
  Only Available in quartus_tan Executable
-Some Commonly Used Commands
  create_timing_netlist
  report_timing
  delete_timing_netlist

Timing Netlist
-Timing Netlist Must Be Created before Reporting
-Use create_timing_netlist Command
-Options
  Minimum Timing Analysis
  Specify Speed Grade of Target Part
  Specify Post-Synthesis Netlist

report_timing Command
-Computes and Reports Timing Paths on the Fly
  Memory Efficient
  Can Report Any Path in Design
      includes Paths not in Timing Report Tables

-Examples

report_timing -tsu
report_timing -clock_setup -clock_filter clk
report_timing -tpd -npaths 5

::quartus::timing Example
-List Paths for All Failing Paths to Two Text Files
  Clock Setup for Maximum Timing Analysis(Default)
  Clock Hold for Minimum Timing Analysis

Example:

load_package timing
project_open fir_filter -revision filtref
create_timing_netlist
report_timing -clock_setup -src_clock_filter clk -clock_filter clkx2 \
  -all_failures -file slow_corner_cross_domain_paths.txt
delete_timing_netlist
create_timing_netlist -fast_model
report_timing -clock_hold -src_clock_filter clk -clock_filter clkx2 \
  -all_failures -file fast_corner_cross_domain_paths.txt
delete_timing_netlist
project_close

::quartus::timing_report Package
-List Timing Paths
  Available in quartus_tan and GUI TCL Console
-One Command
  list_path
-Reports Timing Paths in the Timing Analysis Report
  Applies Only to Pre-computed Paths in Report
  Paths not Shown Cannot Be Reported
-Similar Options as report_timing Command

Example:

list_path -from inst4 -to inst5* -stdout

Pop Quiz
-What Is the Different between These Two Commands?
  report_timing
  list_path

Pop Quiz Answer
-The list_path Command
  Works Only for Paths in Timing Report Panels
-The report_timing Comand
  Works for Any Path in Design Computes Reports Paths on the Fly
-Both Commands Have Similar Options

Conclusion
-Use Quartus II TCL API For Many Common Tasks
-Examples Demonstrate Common Uses