[VC6] 检查MMX和SSE系列指令集的支持级别（最高SSE4.2）

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参考文献——
《Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2 (2A, 2B & 2C): Instruction Set Reference, A-Z》. December 2011.http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.html
《Intel® Processor Identification and the CPUID Instruction》. January 2011. http://developer.intel.com/content/www/us/en/processors/processor-identification-cpuid-instruction-note.html
《AMD64 Architecture Programmer's Manual Volume 3: General Purpose and System Instructions》. December 2011.http://support.amd.com/us/Processor_TechDocs/24594_APM_v3.pdf
《AMD CPUID Specification》. September 2010. http://support.amd.com/us/Embedded_TechDocs/25481.pdf
http://en.wikipedia.org/wiki/CPUID

运行效果——

代码如下——

// SSE系列指令集的支持级别. simd_sse_level 函数的返回值。#define SIMD_SSE_NONE0// 不支持#define SIMD_SSE_11// SSE#define SIMD_SSE_22// SSE2#define SIMD_SSE_33// SSE3#define SIMD_SSE_3S4// SSSE3#define SIMD_SSE_415// SSE4.1#define SIMD_SSE_426// SSE4.2const char*simd_sse_names[] = {"None","SSE","SSE2","SSE3","SSSE3","SSE4.1","SSE4.2",};// 是否支持MMX指令集BOOLsimd_mmx(){const DWORDBIT_DX_MMX = 0x00800000;// bit 23DWORDv_edx;// check processor support__try {_asm {mov eax, 1cpuidmov v_edx, edx}}__except (EXCEPTION_EXECUTE_HANDLER){return FALSE;}if ( v_edx & BIT_DX_MMX ){// check OS support__try {_asm{pxor mm0, mm0// executing any MMX instructionemms}return TRUE;}__except (EXCEPTION_EXECUTE_HANDLER){}}return FALSE;}// 检测SSE系列指令集的支持级别intsimd_sse_level(){const DWORDBIT_D_SSE = 0x02000000;// bit 25const DWORDBIT_D_SSE2 = 0x04000000;// bit 26const DWORDBIT_C_SSE3 = 0x00000001;// bit 0const DWORDBIT_C_SSSE3 = 0x00000100;// bit 9const DWORDBIT_C_SSE41 = 0x00080000;// bit 19const DWORDBIT_C_SSE42 = 0x00100000;// bit 20BYTErt = SIMD_SSE_NONE;// resultDWORDv_edx;DWORDv_ecx;// check processor support__try {_asm {mov eax, 1cpuidmov v_edx, edxmov v_ecx, ecx}}__except (EXCEPTION_EXECUTE_HANDLER){return SIMD_SSE_NONE;}if ( v_edx & BIT_D_SSE ){rt = SIMD_SSE_1;if ( v_edx & BIT_D_SSE2 ){rt = SIMD_SSE_2;if ( v_ecx & BIT_C_SSE3 ){rt = SIMD_SSE_3;if ( v_ecx & BIT_C_SSSE3 ){rt = SIMD_SSE_3S;if ( v_ecx & BIT_C_SSE41 ){rt = SIMD_SSE_41;if ( v_ecx & BIT_C_SSE42 ){rt = SIMD_SSE_42;}}}}}}// check OS support__try {_asm{xorps xmm0, xmm0// executing any SSE instruction}}__except (EXCEPTION_EXECUTE_HANDLER){return SIMD_SSE_NONE;}return rt;}int main(int argc, char* argv[]){int i;BOOLbmmx = simd_mmx();intnsse = simd_sse_level();printf("MMX: %d\n", bmmx);printf("SSE: %d\n", nsse);for(i=1; i<sizeof(simd_sse_names); ++i){if (nsse>=i)printf("\t%s\n", simd_sse_names[i]);}// waitgetch();printf("\n");return 0;}