K60使用flexbus外扩双口RAM

程序：

/*
 * File: flexbus.c
 * Purpose: Example of communicating to an MRAM with the FlexBus
 *              See the readme file for instructions
 */


#include "common.h"


#define GPIO_PIN_MASK      0x1Fu    //0x1f=31,限制位数为0--31有效
#define GPIO_PIN(x)        (((1)<<(x & GPIO_PIN_MASK)))  //把当前位置1




void TWRK60_flexbus_init(void);


#define MRAM_START_ADDRESS (*(vuint8*)(0x60000000))//注意，flexbus的访问地址




uint16 m0;
uint16 m1;
/********************************************************************/
void main (void)
{
uint16 wdata16 = 0x00;
uint16 rdata16 = 0x00;
    uint32 n = 0;
 
      TWRK60_flexbus_init();


    wdata16=0xffff;   //data to write to mram
        m0 = wdata16;
for(n=0x000;n<0x001F;n+=2)  //address offset
{
  *(uint16*)(&MRAM_START_ADDRESS + n) = wdata16;  //write
  rdata16=0x00;  //clear data variable;
  rdata16=(*(uint16*)(&MRAM_START_ADDRESS + n));  //read
                m1 = rdata16;
}



}
/********************************************************************/


void TWRK60_flexbus_init(void){


/* Enable the FlexBus                                               */
/* Configure the FlexBus Registers for 8-bit port size              */
/*  with separate address and data using chip select 0              */
/* These configurations are specific to communicating with          */ 
/*  the MRAM used in this example                                   */
/* For K60 tower module - do not set byte lane shift so that data   */
/*  comes out on AD[31:24]                                          */
  
 //Set Base address
FB_CSAR0 = (uint32)&MRAM_START_ADDRESS;


FB_CSCR0 = FB_CSCR_PS(2) // 16-bit port
| FB_CSCR_AA_MASK // auto-acknowledge
| FB_CSCR_ASET(0x1) // assert chip select on second clock edge after address is asserted
| FB_CSCR_WS(0x1) // 1 wait state - may need a wait state depending on the bus speed
| FB_CSCR_BEM_MASK
| FB_CSCR_RDAH(1);


  FB_CSMR0  =   FB_CSMR_BAM(0x7)  //Set base address mask for 512K address space
              | FB_CSMR_V_MASK    //Enable cs signal
              ;
              
//enable BE signals - note, not used in this example
FB_CSPMCR = FB_CSPMCR_GROUP2(2) | FB_CSPMCR_GROUP3(2);


  //fb clock divider 3
  SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV3(0x3);
   
   
  /* Configure the pins needed to FlexBus Function (Alt 5) */
  /* this example uses low drive strength settings         */


  //address


  PORTC_PCR1  = PORT_PCR_MUX(5);           //  fb_ad[12]
  PORTC_PCR2  = PORT_PCR_MUX(5);           //  fb_ad[11]
  PORTC_PCR4  = PORT_PCR_MUX(5);           //  fb_ad[10]
  PORTC_PCR5  = PORT_PCR_MUX(5);           //  fb_ad[9]
  PORTC_PCR6  = PORT_PCR_MUX(5);           //  fb_ad[8]
  PORTC_PCR7  = PORT_PCR_MUX(5);           //  fb_ad[7]
  PORTC_PCR8  = PORT_PCR_MUX(5);           //  fb_ad[6]
  PORTC_PCR9  = PORT_PCR_MUX(5);           //  fb_ad[5]
  PORTC_PCR10 = PORT_PCR_MUX(5);           //  fb_ad[4]
  PORTD_PCR2  = PORT_PCR_MUX(5);           //  fb_ad[3]
  PORTD_PCR3  = PORT_PCR_MUX(5);           //  fb_ad[2]
  PORTD_PCR4  = PORT_PCR_MUX(5);           //  fb_ad[1]
  PORTD_PCR5  = PORT_PCR_MUX(5);           //  fb_ad[0]
 // PORTD_PCR6  = PORT_PCR_MUX(5);           //  fb_ad[0]，由于某种原因，AD0不能直接作为地址a0用，这个和ub、lb引脚有关
  
  //data
  PORTB_PCR20 = PORT_PCR_MUX(5);           //  fb_ad[31] used as d[15]
  PORTB_PCR21 = PORT_PCR_MUX(5);           //  fb_ad[30] used as d[6]
  PORTB_PCR22 = PORT_PCR_MUX(5);           //  fb_ad[29] used as d[5]
  PORTB_PCR23 = PORT_PCR_MUX(5);           //  fb_ad[28] used as d[4]
  PORTC_PCR12 = PORT_PCR_MUX(5);           //  fb_ad[27] used as d[3]
  PORTC_PCR13 = PORT_PCR_MUX(5);           //  fb_ad[26] used as d[2]
  PORTC_PCR14 = PORT_PCR_MUX(5);           //  fb_ad[25] used as d[1]
  PORTC_PCR15 = PORT_PCR_MUX(5);           //  fb_ad[24] used as d[0]
  PORTB_PCR6 = PORT_PCR_MUX(5);           //  fb_ad[23]used as d[0]
  PORTB_PCR7 = PORT_PCR_MUX(5);           //  fb_ad[22]used as d[0]
  PORTB_PCR8 = PORT_PCR_MUX(5);           //  fb_ad[21]used as d[0]
  PORTB_PCR9 = PORT_PCR_MUX(5);           //  fb_ad[20]used as d[0]
  PORTB_PCR10  = PORT_PCR_MUX(5);           //  fb_ad[19]used as d[0]
  PORTB_PCR11 = PORT_PCR_MUX(5);           //  fb_ad[18]used as d[0]
  PORTB_PCR16 = PORT_PCR_MUX(5);           //  fb_ad[17]used as d[0]
  PORTB_PCR17 = PORT_PCR_MUX(5);           //  fb_ad[16]used as d[0]
 
  


  //control signals
  PORTB_PCR19 = PORT_PCR_MUX(5);          // fb_oe_b
  PORTC_PCR11 = PORT_PCR_MUX(5);          // fb_rw_b  
  PORTD_PCR1  = PORT_PCR_MUX(5);          // fb_cs0_b
 // PORTD_PCR0  = PORT_PCR_MUX(5);          // fb_ale
  


   PORTE_PCR12  = PORT_PCR_MUX(1); 
    PORTE_PCR11  = PORT_PCR_MUX(1); 
     PORTE_PCR10  = PORT_PCR_MUX(1); 
      PORTE_PCR9  = PORT_PCR_MUX(1); 
       PORTE_PCR8  = PORT_PCR_MUX(1); 


  GPIOE_PDDR=GPIO_PDDR_PDD(GPIO_PIN(8)|GPIO_PIN(9)|GPIO_PIN(10));    //定义PORTe的pin12,13,14,15,16,17为输出
  GPIOE_PDOR &= ~GPIO_PDOR_PDO(GPIO_PIN(8)|GPIO_PIN(9));       //ub,lb为低电平
  GPIOE_PDOR |=  GPIO_PDOR_PDO(GPIO_PIN(10)); //IO口输出高电平，/SEM为高电平 
}