7_1_天天向上_FPGA_1

Case语句+优化器
module dircase(a,b,c,d);
input b,c;
input[1:0]a;
output d;
reg d;
always @(a or b or c)
 case(a)//ambit synthesis case=full
 2`b00:d=b;
 2`b01:d=c;
 endcase
endmodule

assign q=(al=1?)d:0;

always@(al or d)
begin
 if(al==1)q<=d;
 else   q<=0;
end

双向口建模 高阻态
module bus_xcvr
(bus_a,bus_b,en_a_b,en_b_a);
inout bus_a,bus_b;
input en_a_b,en_b_a;
bufif1 b1(bus_b,bus_a,en_a_b);
bufif1 b2(bus_a,bus_b,en_b_a);
endmodule

Verilog任务
module top;
 reg clk,a,b;
 DUT ul(out,a,b,clk);
 always #5 clk=!clk;
 task neg_clocks;
  input [31:0]number_of_edges;
  repeat(number_of_edges)@(negedge clk);
 endtask
 initial begin
  clk=0;a=1;b=1;
  neg_clocks(3);//任务调用
  a=0;
  neg_clocks(5);
  b=0;
 end
endmodule