Timing Modeling--时序模型

The cell timing models are intended to provide accurate timing for various instances of the cell in the design environment. The timing models are normally obtained from detailed circuit simulations of the cell to model the actual scenario of the cell operation. The timing models are specified for each

timing arc of the cell.

Let us first consider timing arcs for a simple inverter logic cell shown in Figure 3-1. Since it is an inverter, a rising (falling) transition at the input causes a falling (rising) transition at the output. The two kinds of delay characterized for the cell are:
• Tr : Output rise delay
• Tf : Output fall delay

Notice that the delays are measured based upon the threshold points defined in a cell library , which is typically 50% Vdd. Thus, delays are measured from input crossing its threshold point to the output crossing its threshold point.

The delay for the timing arc through the inverter cell is dependent on two factors:
i. the output load, that is, the capacitance load at the output pin of the inverter, and
ii. the transition time of the signal at the input.

The delay values have a direct correlation with the load capacitance - the larger the load capacitance, the larger the delay. In most cases, the delay increases with increasing input transition time. There are a few scenarios where the input threshold (used for measuring delay) is significantly different from the internal switching point of the cell. In such cases, the delay through the cell may show non-monotonic behavior with respect to the input transition time - a larger input transition time may produce a smaller delay especially if the output is lightly loaded.

The slew at the output of a cell depends mainly upon the output capacitance- output transition time increases with output load. Thus, a large slew at the input (large transition time) can improve at the output depending upon the cell type and its output load. Figure 3-2 shows cases where the transition time at the output of a cell can improve or deteriorate depending on the load at the output of the cell.

1.Linear Timing Model

A simple timing model is a linear delay model, where the delay and the output transition time of the cell are represented as linear functions of the two parameters: input transition time and the output load capacitance. The
general form of the linear model for the delay, D, through the cell is illustrated below.

D = D0 + D1 * S + D2 * C

where D0, D1, D2 are constants, S is the input transition time, and C is the output load capacitance. The linear delay models are not accurate over the range of input transition time and output capacitance for submicron technologies,and thus most cell libraries presently use the more complex models such as the non-linear delay model.

2.Non-Linear Delay Model

Most of the cell libraries include table models to specify the delays and timing checks for various timing arcs of the cell. Some newer timing libraries for nanometer technologies also provide current source based advanced timing models (such as CCS, ECSM, etc.) which are described later in this chapter. The table models are referred to as NLDM (Non-Linear Delay Model) and are used for delay, output slew, or other timing checks. The table models capture the delay through the cell for various combinations of input transition time at the cell input pin and total output capacitance at the cell output.

An NLDM model for delay is presented in a two-dimensional form, with the two independent variables being the input transition time and the output load capacitance, and the entries in the table denoting the delay.

3.时序电路的timing model

For synchronous inputs, such as pin D (or SI, SE), there are the following timing arcs:
i. Setup check arc (rising and falling)
ii. Hold check arc (rising and falling)

For asynchronous inputs, such as pin CDN, there are the following timing
arcs:
i. Recovery check arc
ii. Removal check arc

For synchronous outputs of a flip-flop, such as pins Q or QN, there is the
following timing arc:
i. CK-to-output propagation delay arc (rising and falling)

3.1 Asynchronous Checks

The recovery time is the minimum time that an asynchronous input is stable after being deasserted before the next active clock edge.
Similarly, the removal time is the minimum time after an active clock edge that the asynchronous pin must remain active before it can be de-asserted.

3.2 setup and hold time checks

The setup and hold constraints for a synchronous pin of a sequential cell are normally described in terms of two-dimensional tables as illustrated below. The example below shows the setup and hold timing information
for the data pin of a flip-flop.

pin (D) {
direction : input;
. . .
timing () {
related_pin : "CK";
timing_type : "setup_rising";
rise_constraint ("setuphold_template_3x3") {
index_1("0.4, 0.57, 0.84"); /* Data transition */
index_2("0.4, 0.57, 0.84"); /* Clock transition */
values( /* 0.4 0.57 0.84 */ \
/* 0.4 */ "0.063, 0.093, 0.112", \
/* 0.57 */ "0.526, 0.644, 0.824", \
/* 0.84 */ "0.720, 0.839, 0.930");

} fall_constraint ("setuphold_template_3x3") {
index_1("0.4, 0.57, 0.84"); /* Data transition */
index_2("0.4, 0.57, 0.84"); /* Clock transition */
values( /* 0.4 0.57 0.84 */ \
/* 0.4 */ "0.762, 0.895, 0.969", \
/* 0.57 */ "0.804, 0.952, 0.166", \
/* 0.84 */ "0.159, 0.170, 0.245");
}
}
}

timing () {
related_pin : "CK";
timing_type : "hold_rising";
rise_constraint ("setuphold_template_3x3") {
index_1("0.4, 0.57, 0.84"); /* Data transition */
index_2("0.4, 0.57, 0.84"); /* Clock transition */
values( /* 0.4 0.57 0.84 */ \
/* 0.4 */ "-0.220, -0.339, -0.584", \
/* 0.57 */ "-0.247, -0.381, -0.729", \
/* 0.84 */ "-0.398, -0.516, -0.864");
} fall_constraint ("setuphold_template_3x3") {
index_1("0.4, 0.57, 0.84"); /* Data transition */
index_2("0.4, 0.57, 0.84");/* Clock transition */
values( /* 0.4 0.57 0.84 */ \
/* 0.4 */ "-0.028, -0.397, -0.489", \
/* 0.57 */ "-0.408, -0.527, -0.649", \
/* 0.84 */ "-0.705, -0.839, -0.580");
}
}