Questions when tuning 8168's DDRIII phy.

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/245918.aspx
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Posted by SuitJune Young

onFeb 14 2013 22:03 PM

Intellectual740 points

Hello,We designed a custom DM8168 board using DDRIII RAM.

Now Our Board can run DDRIII at 1333MHz,but CAN'T at 1600MHz.So I want to tune the DDRIII phy using CCS5.1

But I followed the wiki page:http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init#Hardware_and_CCS_Setup

there is a error after the DDR3_SlaveRatio_ByteWiseSearch_TI816x.out file was loaded.

What caused this error?

Thanks for any reply.

br~

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  Posted by BrandonAzbell

  onFeb 14 2013 22:42 PM

  

  Guru54040 points

  This type of error occurs when CCS loads the image file .out as it attempt to find the source file associated with the symbol main() so that you can single step through C source.

  However, the C source was not provided with these utilities.

  You should be able to ignore this message.

  Brandon

  

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  Posted by SuitJune Young

  onFeb 14 2013 23:13 PM

  

  Intellectual740 points

  Thank you,Azbell.

  And accroding to the wiki page,there wil be a print information: such as

  Running the Slave Ratio Search Program

  Run: 

  Enter 0 for DDR Controller 0 & 1 for DDR Controller 1 

  0 

  
  

  Above message doesn't appear in CCS console.Does these appear through UART?

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  Posted by Badri Narayanan

  onFeb 15 2013 01:15 AM

  

  Genius13720 points

  You should see the print in CCS console not in UART>.Did you press F8 to run the application after loading ? Make sure DDR interleaving is disabled and DDR configuration is done correctly by means of GEL file.Did you get any error msgs when loading the out file ?

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  Posted by SuitJune Young

  onFeb 15 2013 02:11 AM

  

  Intellectual740 points

  thank you very much!

  When I press the "F8",it works.

  But there are some unexpected information in console.

  [CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
  [CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
  [CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
  [CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
  [CortexA8] RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
  [CortexA8] RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE

  I calcuate DDR at 800M clock rate.

  But it still get the timing value.

  Does these timing information  will  be right?

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  Posted by Biser Gatchev-XID

  onFeb 15 2013 04:01 AM

  

  Genius16740 points

  The maximum DDR3 frequency is 796MHz (http://processors.wiki.ti.com/index.php/DM816x_AM389x_PSP_U-Boot#Modifying_U-Boot_DDR3_frequency).

  Best Regards

  Biser

  Note:  If this answer solves your question please mark post as "Answered"

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  Posted by SuitJune Young

  onFeb 15 2013 04:13 AM

  

  Intellectual740 points

  sorry that I didn't describe my setting rigorously.

  I entered 796MHz in the ratioseed excel to get the value.

  So why does these "DIDN'T CONVERGE " information appear?

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  Posted by Biser Gatchev-XID

  onFeb 15 2013 08:58 AM

  

  Genius16740 points

  Can you post a copy of the ratio seed excel sheet with your data?

  Best Regards

  Biser

  Note:  If this answer solves your question please mark post as "Answered"

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  Posted by SuitJune Young

  onFeb 15 2013 19:09 PM

  

  Intellectual740 points

  

  the above is my excel.

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  Posted by Biser Gatchev-XID

  onFeb 18 2013 02:34 AM

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  Verified bySuitJune Young

  

  Genius16740 points

  The Excel sheet seems correct. Is this EMIF0 or EMIF1 that's causing problems?

  Best Regards

  Biser

  Note:  If this answer solves your question please mark post as "Answered"

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  Posted by SuitJune Young

  onFeb 18 2013 03:16 AM

  

  Intellectual740 points

  thank you very much.

  "the problem" you mean what?unpected console information or DDR can't run at 1600MHz?

  I suspected there are some issues for excel value so I didn't try.

  Right now I'll try makeing DDRIII run at 1600MHz. 

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  Posted by Biser Gatchev-XID

  onFeb 18 2013 03:30 AM

  

  Genius16740 points

  I mean the "non-converging" problem.

  Best Regards

  Biser

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  Posted by SuitJune Young

  onFeb 18 2013 06:06 AM

  

  Intellectual740 points

  This sheet is for EMIF0,and I have another excel sheet for EMIF1.
  Both these have the "non-converging" problem.But both at last the Program will get the min/opt/max value for DDRIII run at 1600MHz.

   

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  Posted by Badri Narayanan

  onFeb 18 2013 06:08 AM

  

  Genius13720 points

  Did you disable EMIF interleaving before you ran the SW leveling out file ?

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  Posted by SuitJune Young

  onFeb 18 2013 18:59 PM

  

  Intellectual740 points

  NO.how to disable EMIF inerleaving by using CCS?

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  Posted by Badri Narayanan

  onFeb 19 2013 01:51 AM

  

  Genius13720 points

  In TI816x_DDR3.gel, change

  EMIF4PRCM() {

    WR_MEM_32(DMM_LISA_MAP__0, 0x80640300); /* Interleaved 1GB section from 0x80000000*/
    WR_MEM_32(DMM_LISA_MAP__1, 0xC0640320); /* Interleaved 1GB section from 0xC0000000*/
  
    WR_MEM_32(DMM_LISA_MAP__2, 0x80640300);
    WR_MEM_32(DMM_LISA_MAP__3, 0xC0640320);

  to

    WR_MEM_32(DMM_LISA_MAP__0, 0x80500100);
  
    WR_MEM_32(DMM_LISA_MAP__1, 0xC0500120);
  
   
    /*Program the DMM to Access EMIF1*/
  
    WR_MEM_32(DMM_LISA_MAP__2, 0xA0500200);
  
    WR_MEM_32(DMM_LISA_MAP__3, 0xE0500220);

  Make sure you close and reopen CCS and redo the procedure after modifying the GEL.