What is metastability?

1 什么是亚稳态？

如果一个触发器的输入不满足建立时间和保持时间的要求时，触发器的输出就进入了一个不确定的状态（也就是亚稳态）。亚稳态最后有可能是1也有可能是0，整个这个过程叫做亚稳态。如下图所示Tsu是建立时间、Th是保持时间，当触发器的输入信号D不满足建立时间和保持时间的要求时，会出现亚稳态。

如果触发器进入亚稳态，如下图所示：输出会在0和1之间振荡（这里最终输出稳定到0），可以看到在输出稳定之前花了很长时间在振荡（这个时间依赖于触发器的性能）。

在触发器建立时间和保持时间没有满足时，我们来看一下触发器内部的工作状态，以上升沿D触发器为例，当时钟上升沿正好发生在触发器的输入D正准备给master latch传递数据的时候（也就是说时钟上升沿来的时候，想要通过触发器传递的数据正好来），这时触发器最有可能进入亚稳态，This rising clock causes the master latch to try to capture its current value while the slave latch is opened allowing the Q output to follow the "latched" value of the master. The most perfectly "caught" quasi-stable state (on the very top of the hill) results in the longest time required for the flip-flop to resolve itself to one of the stable states.

2 亚稳态持续时间长短

如上图所示，处于稳定状态的逻辑0和逻辑1要比亚稳态稳定很多。理论上处于亚稳态的触发器会持续处于亚稳态，但是实际中它不会持续处于亚稳态，正如在空气中皮球不会来回振荡一样，热和噪声最终会使亚稳态最终趋于0或者1（不确定最终会是哪个）。

3 亚稳态出现的原因

当一个触发器输入的建立时间和保持时间不满足时，会出现亚稳态，下面我们需要知道建立时间和保持时间需要满足多长时间。

• 当输入信号是一个不对称信号时
• 当时钟skew/slew太大时（上升时间和下降时间太大时）
• 处于两个时钟域的接口电路、同一时钟内不同相位的电路
• when the combinational delay is such that flip-flop data input changes in the critical window(setup+hold window)

4 什么是MTBF

MTBF是平均无故障时间，也就是平均两次故障之间的时间，下图给出了一个触发器的MTBF以及MTBF等式。

 5 我们该怎么避免出现亚稳态

In reality, one cannot avoid metastability and increased clock-to-Q delays in synchronizing asynchronous inputs, without the use of tricky self-timed circuits. So a more appropriate question might be"怎么最大程度容忍亚稳态".

设计者可以使用的最简单的方法是提高时钟周期（也就是降低时钟频率），This approach ,while simple,is rarely practical given the performance requirements of most modern designs.

The most common way to tolerate metastabiligy is to add one or more successive synchronizing flip-flops to the synchronizer.This approach allows for an entire clock period(except for the setup time of the second flip-flop) for metastable events in the first synchronizing flip-flop to resolve themselves. This does,however,increase the latency in the synchronous logic's observation of input changes.

Neither of these approaches can guarantee that metastabiligy cannot pass through the synchronizer;they simply reduce the probability to practical levels.

In quantitative terms,if the MTBF of a particular flip-flop in the context of a given clock rate and input transition rate is 33.33seconds then the MTBF of two such flip-flops used to synchronize the input would be(33.33* 33.33) = 18.514 Minutes. Well I have taken the worst flip-flop ever designed in history of man kind :-). The figure below shows how to connect two flip-flops in series to achieve this and also the resultant MTBF.

Normally,

• we can use a metastable hardened flip-flop
• cascade two or three DFF

参考文献

• http://www-s.ti.com/sc/psheets/sdya006/sdya006.pdf
• Thomas J. Chaney, "Measured Flip-Flop Responses to Marginal Triggering", IEEE Transactions on Computers, Vol. C-32. No. 12, December 1983, pp.1207-1209.
• Lindsay Kleeman and Antonio Cantoni, "On the Unavoidability of Metastable Behavior in Digital Systems", IEEE Transactions on Computers, Vol. C-36. No. 1, January 1987, pp.109-112.
• Lindsay Kleeman and Antonio Cantoni, "Can Redundancy and Masking Improve the Performance of Synchronizers?", IEEE Transactions on Computers, Vol. C-35, No. 7, July 1986, pp.643-646.
• Cypress Semiconductor, "Are Your PLDs Metastable?, Fax ID: 6403, May 1992, Revised March 6,1997. http://www.cypress.com/pld/pldappnotes.html#pldmeta
• http://www.xilinx.com/apps/xapp.htm
• M. Valencia, M. J. Bellido, J. L. Huertas, A. J. Acosta, and S. Sanchez-Solano, "Modular Asynchronous Arbiter Insensitive to Metastability. IEEE Transactions on Computers, 44(12):1456-1461, December 1995