AM335X DDR 3 调试总结

Author:DriverMonkey

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因为开发上的用的是DDR2 而我们项目中用的是DDR3，所以需要我们进行修改

1. 刚开始调试的时候按照TI FAE 给的文档调试 DDR3（文档名：DDR3 Software Leveling and Registers Configuration.pdf 作者：garry）

     但是一直有问题，卡在了用CCS5 运行 DDR3_slave_ratio_search_auto.out 这个软件的时候 老是进入了死循环

2. 继续找资料，最后在github 上找到了一个用DDR3例子

3. 移植例子，系统起来

以下是我移植的代码：

#define DDR3_EMIF_READ_LATENCY  0x100006    /* Enable Dynamic Power Down */#define DDR3_EMIF_TIM10x0888A39B#define DDR3_EMIF_TIM20x26337FDA#define DDR3_EMIF_TIM30x501F830F#define DDR3_EMIF_SDCFG 0x61C04AB2#define DDR3_EMIF_SDREF 0x0000093B#define DDR3_ZQ_CFG 0x50074BE4#define DDR3_DLL_LOCK_DIFF0x1#define DDR3_RATIO0x40#define DDR3_INVERT_CLKOUT0x1#define DDR3_RD_DQS 0x3B#define DDR3_WR_DQS 0x85#define DDR3_PHY_WR_DATA0xC1#define DDR3_PHY_FIFO_WE0x100#define DDR3_IOCTRL_VALUE0x18B/* Micron ???? on 1.5 and later EVMs */#define DDR3_EMIF_TIM2_EVM0x26517FDA#define DDR3_EMIF_TIM3_EVM0x501F851F#define DDR3_RD_DQS_EVM 0x3A#define DDR3_WR_DQS_EVM 0x0CD#define DDR3_PHY_FIFO_WE_EVM0x10B#define DDR3_PHY_WR_DATA_EVM0x106#define DATA1_RD_DQS_SLAVE_RATIO_0(DDR_PHY_BASE_ADDR + 0x16C)#define EMIF0_0_ZQ_CONFIG(EMIF4_0_CFG_BASE + 0xC8)#define DATA1_WR_DQS_SLAVE_RATIO_0      (DDR_PHY_BASE_ADDR + 0x180)#define DATA1_FIFO_WE_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x1AC)#define DATA1_WR_DATA_SLAVE_RATIO_0     (DDR_PHY_BASE_ADDR + 0x1C4)#define MDDR_SEL_DDR2           0xefffffff              /* IOs set for DDR2-STL Mode */#define CKE_NORMAL_OP           0x00000001              /* Normal Op:CKE controlled by EMIF */static void config_emif_ddr3(void){        /*Program EMIF0 CFG Registers*/writel(DDR3_EMIF_READ_LATENCY, EMIF4_0_DDR_PHY_CTRL_1);writel(DDR3_EMIF_READ_LATENCY, EMIF4_0_DDR_PHY_CTRL_1_SHADOW);writel(DDR3_EMIF_READ_LATENCY, EMIF4_0_DDR_PHY_CTRL_2);writel(DDR3_EMIF_TIM1, EMIF4_0_SDRAM_TIM_1);writel(DDR3_EMIF_TIM1, EMIF4_0_SDRAM_TIM_1_SHADOW);writel(DDR3_EMIF_TIM2, EMIF4_0_SDRAM_TIM_2);writel(DDR3_EMIF_TIM2, EMIF4_0_SDRAM_TIM_2_SHADOW);writel(DDR3_EMIF_TIM3, EMIF4_0_SDRAM_TIM_3);writel(DDR3_EMIF_TIM3, EMIF4_0_SDRAM_TIM_3_SHADOW);writel(DDR3_EMIF_SDREF, EMIF4_0_SDRAM_REF_CTRL);writel(DDR3_EMIF_SDREF, EMIF4_0_SDRAM_REF_CTRL_SHADOW);writel(DDR3_ZQ_CFG, EMIF0_0_ZQ_CONFIG);writel(DDR3_EMIF_SDCFG, EMIF4_0_SDRAM_CONFIG);  }#ifndef PRCM_MOD_EN#define PRCM_MOD_EN0x2#endifvoid enable_ddr3_clocks(void){/* Enable the  EMIF_FW Functional clock */writel(PRCM_MOD_EN, CM_PER_EMIF_FW_CLKCTRL);/* Enable EMIF0 Clock */writel(PRCM_MOD_EN, CM_PER_EMIF_CLKCTRL);/* Poll if module is functional */while ((readl(CM_PER_EMIF_CLKCTRL)) != PRCM_MOD_EN);}static void phy_config_cmd(void){writel(DDR3_RATIO, CMD0_CTRL_SLAVE_RATIO_0);writel(DDR3_INVERT_CLKOUT, CMD0_INVERT_CLKOUT_0);writel(DDR3_RATIO, CMD1_CTRL_SLAVE_RATIO_0);writel(DDR3_INVERT_CLKOUT, CMD1_INVERT_CLKOUT_0);writel(DDR3_RATIO, CMD2_CTRL_SLAVE_RATIO_0);writel(DDR3_INVERT_CLKOUT, CMD2_INVERT_CLKOUT_0);}static void phy_config_data(void){writel(DDR3_RD_DQS, DATA0_RD_DQS_SLAVE_RATIO_0);writel(DDR3_WR_DQS, DATA0_WR_DQS_SLAVE_RATIO_0);writel(DDR3_PHY_FIFO_WE, DATA0_FIFO_WE_SLAVE_RATIO_0);writel(DDR3_PHY_WR_DATA, DATA0_WR_DATA_SLAVE_RATIO_0);writel(DDR3_RD_DQS, DATA1_RD_DQS_SLAVE_RATIO_0);writel(DDR3_WR_DQS, DATA1_WR_DQS_SLAVE_RATIO_0);writel(DDR3_PHY_FIFO_WE, DATA1_FIFO_WE_SLAVE_RATIO_0);writel(DDR3_PHY_WR_DATA, DATA1_WR_DATA_SLAVE_RATIO_0);}static void config_am335x_ddr3(void){enable_ddr3_clocks();config_vtp(); phy_config_cmd();phy_config_data();/* set IO control registers */writel(DDR3_IOCTRL_VALUE, DDR_CMD0_IOCTRL);writel(DDR3_IOCTRL_VALUE, DDR_CMD1_IOCTRL);writel(DDR3_IOCTRL_VALUE, DDR_CMD2_IOCTRL);writel(DDR3_IOCTRL_VALUE, DDR_DATA0_IOCTRL);writel(DDR3_IOCTRL_VALUE, DDR_DATA1_IOCTRL);/* IOs set for DDR3 */writel(readl(DDR_IO_CTRL) & MDDR_SEL_DDR2, DDR_IO_CTRL);/* CKE controlled by EMIF/DDR_PHY */writel(readl(DDR_CKE_CTRL) | CKE_NORMAL_OP, DDR_CKE_CTRL);config_emif_ddr3(); }